Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - Altera SDRAM Verilog

Search list

[Other resource] sdr sdram controller

Description: ALTERA sdram vhdl与verilog参考设计-Altera SDRAM VHDL and Verilog reference design
Platform: | Size: 2459435 | Author: 陈东平 | Hits:

[Other resource] Sdram_Control_4Port

Description: ALTERA 的关于对SDRAM控制器操作的verilog相关程序，很不错绝对值得借鉴。
Platform: | Size: 13230 | Author: 邹振兴 | Hits:

[VHDL-FPGA-Verilog] sdr sdram controller

Description: ALTERA sdram vhdl与verilog参考设计-Altera SDRAM VHDL and Verilog reference design
Platform: | Size: 2458624 | Author: 陈东平 | Hits:

[VHDL-FPGA-Verilog] Sdram_Control_4Port

Description: ALTERA 的关于对SDRAM控制器操作的verilog相关程序，很不错绝对值得借鉴。-ALTERA on the operation of the SDRAM controller Verilog procedures, it is definitely worth a good draw.
Platform: | Size: 13312 | Author: 邹振兴 | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-verilog

Description: 标准SRD SDRAM控制器参考设计，altera提供 Verilog代码,带有使用手册，大家试试交流一下 -Standard SRD SDRAM controller reference design, altera provide Verilog code, with user manual, we try to exchange some
Platform: | Size: 776192 | Author: 费尔德 | Hits:

[VHDL-FPGA-Verilog] AlteraSDR-SDRAM

Description: Altera 官方提供的SDRAM控制器,verilog的-SDRAM controller provided by Altera in Verilog HDL
Platform: | Size: 811008 | Author: machenghai | Hits:

[VHDL-FPGA-Verilog] Altera_DDR_controller_core

Description: Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, description documents, DDR verilog model and simulation testbench are all included.
Platform: | Size: 752640 | Author: 沈志 | Hits:

[VHDL-FPGA-Verilog] sdr-sdram-(verilog)

Description: Altera的SDR SDRAM模型，verilog实现，带说明书文件以及仿真文件、SDRAM原型文件。-Altera' s SDR SDRAM model, verilog implementation, with manual files and simulation files, SDRAM prototype file.
Platform: | Size: 777216 | Author: 左左 | Hits:

[VHDL-FPGA-Verilog] SDR_SDRAM_IP

Description: SDR SDRAM 控制器，Altera官网重要资料。内涵说明文档，和VHDL与Verilog两种设计IP。-SDR SDRAM controller from Altera
Platform: | Size: 2360320 | Author: peteryu010 | Hits:

[VHDL-FPGA-Verilog] dab1814114c3

Description: 此為採用ALTERA所做的DDR 控制器(verilog)- File/Directory Description ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation Contains the verilog testbench, modelsim project file, and library \source Contains the verilog source files for the DDR SDRAM reference design \synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
Platform: | Size: 880640 | Author: 李志偉 | Hits:

[VHDL-FPGA-Verilog] Altera-SDRAM_controller-IP-CORE

Description: ALTRA官方提供的SDRAM的控制内核，VHDL和VERILOG版本都有，希望对大家有用-The ALTRA official SDRAM control kernel, VHDL and VERILOG version have the hope that useful
Platform: | Size: 2378752 | Author: mr jiang | Hits:

[VHDL-FPGA-Verilog] my_test_rw_pack9

Description: 基于Verilog HDL的SDRAM控制器。 实验条件： 工具：Quartus II 6.0 ,SignalTap II FPGA：Altera Cyclone EP1C12Q240C8N SDRAM：HY57V283220T-6-SDRAM controller based on Verilog HDL. Experimental conditions: Tools: Quartus II 6.0, SignalTap II FPGA: Altera Cyclone EP1C12Q240C8N SDRAM: HY57V283220T-6
Platform: | Size: 3520512 | Author: TYS | Hits:

[Other] sdr-sdram-verilog

Description: SDRAM IP CORE,ALTERA提供-SDRAM IP CORE,ALTERA
Platform: | Size: 1277952 | Author: wushj | Hits:

[VHDL-FPGA-Verilog] 61EDA_C915

Description: altera公司的SDRAM 控制器的ip core源代码 里面包含verilog及vhdl两种语言编写的 方便选择-altera company SDRAM controller ip core source code which contains verilog and vhdl two kinds of language for easy selection
Platform: | Size: 2325504 | Author: 杜小方 | Hits:

[VHDL-FPGA-Verilog] SDRAM_96M_UART_TestOK

Description: SDRAM_96M_串口实验OK 一个项目工程，硬件包含Altera FPGA，SDRAM，串口，使用verilog-SDRAM_96M_ serial experiments OK a project engineering, hardware contains Altera FPGA, SDRAM, serial port, using verilog
Platform: | Size: 989184 | Author: 李家发 | Hits:

[VHDL-FPGA-Verilog] DACtoADCtoSPI_Triangle1

Description: DACtoADCtoSPI_Triangle1.zip 一个项目工程，硬件包含Altera FPGA，SDRAM，串口，使用verilog-DACtoADCtoSPI_Triangle1.zip a project engineering, hardware contains Altera FPGA, SDRAM, serial port, using verilog
Platform: | Size: 121856 | Author: 李家发 | Hits:

[VHDL-FPGA-Verilog] ALTERA_FPGA_SDRAM

Description: 使用ALTERA的FPGA控制SDRAM的verilog程序-Use ALTERA s FPGA to control SDRAM s verilog program
Platform: | Size: 13050880 | Author: 李 | Hits:

[VHDL-FPGA-Verilog] my_sdram_mdl

Description: 此功能为altera fpga 的sdram 控制器，串口接收与发送(This feature altera fpga sdram controller, serial port to receive and send)
Platform: | Size: 1206272 | Author: flyhouse112 | Hits:

[VHDL-FPGA-Verilog] sdr_sdram

Description: sdram使用接口仿真，altera公司ip使用方法(sdram verilog. SDRAM using interface simulation, Altera company IP use method)
Platform: | Size: 12288 | Author: 风雪来 | Hits:

CodeBus www.codebus.net