Search - Altera VHDL

Search - Altera VHDL - List

[SourceCode] altera sdram controller DL : 1: altera sdram controller vhdl
Update : 2011-03-17 Size : 2.26mb Publisher : langzhongfeilang@126.com
[VHDL-FPGA-Verilog] 8255 DL : 0: 8255参考设计VHDL源代码-The sound code of 8255 reference design based on VHDL
Update : 2025-02-17 Size : 221kb Publisher :
[VHDL-FPGA-Verilog] mc8051_cyclone_nios DL : 0: 增强型8051的VHDL源代码，两个周期执行一条指令，仿真工具为Modelsim，开发板为Altera的EP1C20开发板-enhanced 8051 VHDL source code, the implementation of a two-cycle instruction, simulation tools for Modelsim, development board for the Altera EP1C20 development board
Update : 2025-02-17 Size : 1.91mb Publisher : 柳如飞
[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl DL : 0: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Update : 2025-02-17 Size : 758kb Publisher : 张涛
[VHDL-FPGA-Verilog] I2C总线控制器 altera提供-VHDL DL : 0: I2C总线控制器 altera提供的VHDL的源程序代码-I2C Bus Controller ALTERA the VHDL source code
Update : 2025-02-17 Size : 1.56mb Publisher : 陈旭
[ARM-PowerPC-ColdFire-MIPS] Altera的IP源码8237 DL : 0: 名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持-renowned name of the company Synopsys 8051IP Core VHDL language, support can be keilC51
Update : 2025-02-17 Size : 203kb Publisher : 上面的
[VHDL-FPGA-Verilog] seq_gen_576 DL : 0: 高清电视HDTV信号发生器，576P逐行，VHDL语言，ALTERA的Quartus II开发平台-HDTV HDTV signal generator, 576P progressive, VHDL, Altera's Quartus II development platform
Update : 2025-02-17 Size : 158kb Publisher : lidan
[Other] DesignofVeryDeepPipelinedMultipliersforFPGAs(IEEE) DL : 0: 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed.
Update : 2025-02-17 Size : 175kb Publisher : 李中伟
[Other] ref-ddr-sdram-vhdl DL : 0: 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
Update : 2025-02-17 Size : 427kb Publisher : kevin
[Other Embeded program] altera_USB_blaste DL : 0: altera USB blaste 制作全套资料。包括原理图、93LC46的配置文件和CPLD的VHDL源程序。-altera USB blaste produced full set of information. Including drawings, 93LC46 configuration files and CPLD VHDL source.
Update : 2025-02-17 Size : 134kb Publisher : xuphone
[VHDL-FPGA-Verilog] cpu-leon3-altera-ep1c20 DL : 0: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了在Altera公司的ep1c20 FPGA的位码文件和配置文件，可以直接下载使用！-A VHDL design with the use of powerful 32-bit CPU, this document contains Altera Corporation in the ep1c20 FPGA code and configuration files, you can direct download!
Update : 2025-02-17 Size : 671kb Publisher : zhao onely
[VHDL-FPGA-Verilog] cpu-leon3-altera-ep2s60-ddr DL : 0: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的DDR控制器程序！-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of DDR controller program!
Update : 2025-02-17 Size : 735kb Publisher : zhao onely
[Other] ALTERA-USB-BLASTER DL : 0: ALTERA-USB-BLASTER is a pdf file which is dawed by protel.
Update : 2025-02-17 Size : 18kb Publisher : hewen1983
[VHDL-FPGA-Verilog] add_3p DL : 0: 3级流水线，含4元件的22位全加器的VHDL语言实现，适用于altera系列的FPGA-3-stage pipeline, with 4 components of 22 full adder realize the VHDL language, applicable to altera Series FPGA
Update : 2025-02-17 Size : 2kb Publisher : wgx
[VHDL-FPGA-Verilog] RS422 DL : 1: 这是一个用VHDL开发的RS422通讯程序,在ALTERA FLEX EPF10K上通过了测试-This is a VHDL development with RS422 communication procedures, in the ALTERA FLEX EPF10K passed the test
Update : 2025-02-17 Size : 1.51mb Publisher : 徐
[VHDL-FPGA-Verilog] PictureBrowser.tar DL : 0: PictureBrowser 是基于Altera 的DE2 开发板设计图像浏览器，代码是VHDL的-PictureBrowser is based on Altera
Update : 2025-02-17 Size : 1.95mb Publisher : 李斌
[VHDL-FPGA-Verilog] ALTERA DL : 0: altera中文的器件选型手册，大家开发fpga采用altera的器件的话可以-altera Chinese manual device selection, the development of U.S. altera FPGA device used, then can
Update : 2025-02-17 Size : 690kb Publisher : zhangxi
[VHDL-FPGA-Verilog] Example-b8-1 DL : 0: 使用ModelSim对Altera设计进行功能仿真对于没有使用到Altera的MegaWizard或LPM的设计而言，功能仿真比较简单，读者只需依据8.2.5小节描述的步骤依次执行即可，对于使用了MegaWizard或LPM的设计，则必需在仿真时指定相关的Altera库-Altera use ModelSim for functional simulation for designs that do not use Altera
Update : 2025-02-17 Size : 3.74mb Publisher : king
[ARM-PowerPC-ColdFire-MIPS] Altera DL : 0: 利用Nios Ⅱ软核处理器，以Altera公司的UP3开发板为硬件平台，以Quartus II、Quartus ID为软件开发平台，设计一个电子钟，实现下列系统功能：（1）在液晶屏上显示时间、日期、状态提示；（2）利用4个按键对时间（时分秒）、日期（年月日）进行设置；（3）利用一个LED灯指示当前设置状态；-The use of soft-core processor, Nios Ⅱ to Altera s UP3 development board as the hardware platform to Quartus II, Quartus ID for software development platform, design a clock
Update : 2025-02-17 Size : 6.16mb Publisher : Emma
[VHDL-FPGA-Verilog] VHDL-FPGA-xilinx-altera-frily DL : 1: VHDL的经典经验。相当的不错，一个多年开发FPGA的工程师自己的记录，适用于ALTERA,XILINX,LATTICE等FPGA的开发。希望对大家有用。-VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera
Update : 2025-02-17 Size : 3.73mb Publisher : 何思涵

« 12 3 4 5 6 7 8 9 10 ... 32 »