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[VHDL-FPGA-Verilog] assembler

Description: PicoBlaze的开发压缩包,PicoBlaze的编译器.-PicoBlaze Development compressed packet, PicoBlaze compiler.
Platform: | Size: 78848 | Author: mao | Hits:

[VHDL-FPGA-Verilog] mcpu_1.06b

Description: MCPU is a minimal cpu aimed to fit into a 32 Macrocell CPLD - one of the smallest available programmable logic devices. While this CPU is not powerful enough for real world applications it has proven itself as a valuable educational tool. The source code is just a single page and easily understood. Both VHDL and Verilog versions are supplied. The package comes with assembler, emulator and extensive documentation.-MCPU is a minimal cpu aimed to fit into a 32 Macrocell CPLD- one of the smallest available programmable logic devices. While this CPU is not powerful enough for real world applications it has proven itself as a valuable educational tool. The source code is just a single page and easily understood. Both VHDL and Verilog versions are supplied. The package comes with assembler, emulator and extensive documentation.
Platform: | Size: 248832 | Author: eldis | Hits:

[ELanguage] webcpp

Description: 将源代码转换成html,支持多操作系统，支持多种编程语言:Ada95, ASP, Assembler, Basic, C, C#, C++, Cg, CLIPS, Fortran, Haskell, Java, Markup, Modula2, Objective C, Pascal, Perl, PHP, Python, Renderman, Ruby, SQL, Tcl- Webcpp converts Ada95, ASP, Assembler, Basic, C, C#, C++, Cg, CLIPS, Fortran, Haskell, Java, Markup, Modula2, Objective C, Pascal, Perl, PHP, Python, Renderman, Ruby, SQL, Tcl, Unix shell, UnrealScript & VHDL into HTML with syntax highlighting and themes
Platform: | Size: 248832 | Author: 杨天 | Hits:

[VHDL-FPGA-Verilog] c16_latest.tar

Description: c16 ucore. this a 16 VHDL cpu core. complete with Assembler and C compiler. All src code included.-c16 ucore. this a 16 VHDL cpu core. complete with Assembler and C compiler. All src code included.
Platform: | Size: 1711104 | Author: vtaranti | Hits:

[VHDL-FPGA-Verilog] servomat

Description: antidad_a EQU s0 talto EQU s1 Rename register sX with <name> tbajo EQU s2 indicador EQU s3 cantidad_b EQU S4 Define constant <name>, assign value name ROM output file generated by pBlazIDE assembler VHDL "ROM_form.vhd", "servo.vhd","servo" grados DSIN 50 pwm DSOUT 100 Create output port, assign port address <name> DSIO <port_id> Create readable output port, assign port address ORG 0 Programs always start at reset vector 0 EINT If using interrupts, be sure to enable the INTERRUPT input Inicio: <<< your code here >>> load talto,0 load tbajo,0 in cantidad_a,grados-antidad_a EQU s0 talto EQU s1 Rename register sX with <name> tbajo EQU s2 indicador EQU s3 cantidad_b EQU S4 Define constant <name>, assign value name ROM output file generated by pBlazIDE assembler VHDL "ROM_form.vhd", "servo.vhd","servo" grados DSIN 50 pwm DSOUT 100 Create output port, assign port address <name> DSIO <port_id> Create readable output port, assign port address ORG 0 Programs always start at reset vector 0 EINT If using interrupts, be sure to enable the INTERRUPT input Inicio: <<< your code here >>> load talto,0 load tbajo,0 in cantidad_a,grados
Platform: | Size: 1057792 | Author: Jorge | Hits:

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