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Description: BIST test doing project, in verilog.
Platform: |
Size: 826368 |
Author: kk |
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Description: A simple BIST in VHDL.
It contains a LFSR with an SISR.
Platform: |
Size: 405504 |
Author: bommeren |
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Description: Mem bist Verilog Module
Platform: |
Size: 107520 |
Author: jc |
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