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Description: 用VHDL语言将二进制数据转换成十进制数据，并将十进制的每一个位分离出来单独存放。使用状态机实现，程序简单，仿真效果很理想，占用可编程器件的资源较少。
Platform: |
Size: 983 |
Author: yato_logo |
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Description: 用VHDL语言将二进制数据转换成十进制数据，并将十进制的每一个位分离出来单独存放。使用状态机实现，程序简单，仿真效果很理想，占用可编程器件的资源较少。-VHDL language with the binary data into decimal data and decimal places separated from each store individually. Realize the use of state machine, the program is simple, simulation results are satisfactory, occupation of programmable devices have fewer resources.
Platform: |
Size: 1024 |
Author: yato_logo |
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Description: Dim tep As String
Dim temp As String
Dim i As Integer
Dim B As Integer
Dim rems As String
tep = rmsg
i = Len(tep)
If i < 1 Then Exit Function
B = i / 2
If i = B * 2 Then
tep = Left(tep, B * 2)
Else
B = B - 1
tep = Left(tep, B * 2)
End If
chg7 = ""
rems = ""
Dim trint As Integer
Dim strtmp As String
trint = 1
strtmp = ""
For i = 1 To B
temp = "&H" & Mid(tep, (i - 1) * 2 + 1, 2)
temp = D_To_B(Val(temp)) 转二进制
If Len(temp) < 8 Then
temp = strpla(8 - Len(temp)) + temp
End If
strtmp = Mid(temp, trint + 1, 8 - trint) + rems
rems = Mid(temp, 1, trint)
chg7 = chg7 & ChrW(CInt(Val(B_To_D(strtmp))))
trint = trint + 1
If trint = 8 Then
trint = 1
chg7 = chg7 & ChrW(CInt(Val(B_To_D(rems))))
rems = ""
End If
Next i- Dim tep As String
Dim temp As String
Dim i As Integer
Dim B As Integer
Dim rems As String
tep = rmsg
i = Len(tep)
If i < 1 Then Exit Function
B = i/2
If i = B* 2 Then
tep = Left(tep, B* 2)
Else
B = B- 1
tep = Left(tep, B* 2)
End If
chg7 = ""
rems = ""
Dim trint As Integer
Dim strtmp As String
trint = 1
strtmp = ""
For i = 1 To B
temp = "&H" & Mid(tep, (i- 1)* 2+ 1, 2)
temp = D_To_B(Val(temp)) 转二进制
If Len(temp) < 8 Then
temp = strpla(8- Len(temp))+ temp
End If
strtmp = Mid(temp, trint+ 1, 8- trint)+ rems
rems = Mid(temp, 1, trint)
chg7 = chg7 & ChrW(CInt(Val(B_To_D(strtmp))))
trint = trint+ 1
If trint = 8 Then
trint = 1
chg7 = chg7 & ChrW(CInt(Val(B_To_D(rems))))
rems = ""
End If
Platform: |
Size: 34816 |
Author: 阿基米德 |
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Description: 二进制转BCD码程序，可作为7段数码管显示的编解码程序，VHDL编写的FPGA工程。-BCD binary code change process, as 7 digital display codec process, VHDL FPGA project prepared.
Platform: |
Size: 1009664 |
Author: 程光 |
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