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Description: 这用java语言模拟一个银行的操作系统,main-class:run 图形界面模式:加参数-graphic 文字模式:加参数-text Client.txt存放客户信息 Compte.txt存放账户信息 Operation.txt账号使用信息 这个版本是法语版的-this java language simulation with a bank of the operating system, main-class : run graphical interface model : Add parameters - graphic text mode : Add parameter-text Client.txt Compte.txt stored customer information stored account information Operation.txt account information using this version is the French version
Platform: | Size: 64361 | Author: | Hits:

[Windows Developbank

Description: 基于c++的排队论问题,MM1∞模型的模拟实现,银行排队模拟-Based on queuing theory c++, the simulation model implementation MM1 ∞
Platform: | Size: 405504 | Author: liz | Hits:

[Software Engineering00245755

Description: The paper discusses the simulation, performance and optimum design of single-phase-to- 2-phase cycloconvertors driving an induction motor. Bridge and centre-tapped circuits using triacs with double-integral control are considered. Results are presented for 2-pole induction-motor drives which may operate at speeds 0 to 1500 rev/min. The simulation is shown to model the performance of the drives successfully, and is used to predict an optimum design. An improvement to the control algorithm at bank crossover is presented. The bridge circuit is more efficient than the centre-tapped circuit, but uses more triacs.-The paper discusses the simulation, performance and optimum design of single-phase-to- 2-phase cycloconvertors driving an induction motor. Bridge and centre-tapped circuits using triacs with double-integral control are considered. Results are presented for 2-pole induction-motor drives which may operate at speeds 0 to 1500 rev/min. The simulation is shown to model the performance of the drives successfully, and is used to predict an optimum design. An improvement to the control algorithm at bank crossover is presented. The bridge circuit is more efficient than the centre-tapped circuit, but uses more triacs.
Platform: | Size: 584704 | Author: behzad farhadi | Hits:

[Banking simulation

Description: 假设某银行有四个窗口对外接待客户,从早晨银行开门起不断有客户进入银行。由于每个窗口在某个时刻只能接待一个客户,因此在客户人数众多时需在每个窗口前顺次排队,对于刚进入银行的客户,如果某个窗口的业务员正空闲,则可上前办理业务,反之,若四个窗口均有客户所占,他便会排在人数最少的队伍后面。现在需要编制程序以模拟银行的这种业务活动并计算一天中客户在银行逗留的平均时间。(Suppose a bank has four windows to receive customers, and from the morning bank opens, there are always customers entering the bank. Because each window to receive a customer at one time only, so in a large number of customers to line up in front of every window, for entering the bank customers, if a window salesman is free, you can come forward for business, on the other hand, if the four windows are for customers, he will be in the back row of the minimum number of teams. Procedures are now needed to model the business activities of the bank and calculate the average time of the customer's stay in the bank during the day.)
Platform: | Size: 12288 | Author: 陌上人如玉 | Hits:

[LabViewstate machine_bank access

Description: 在labview平台通过状态机模型实现模拟银行存取功能。(Simulation bank access function realized by state machine model.)
Platform: | Size: 129024 | Author: 49943 | Hits:

[VHDL-FPGA-Verilogddr_sdram

Description: 包含ddr_sdr_conf_pkg.vhd,reset.vhd,ddr_dcm.vhd,user_if.vhd,ddr_sdram.vhd,Mt46v16m16.vhd以及仿真TB文件;设计采用Virtex ii系列芯片,DDR_SDRAM型号为Mt46v16m16,可用于进行DDR控制的初步学习使用;通过细致了解并进行逻辑控制,可深入理解DDR芯片内部构造; 支持133MHz系统时钟频率,突发长度为2,可进行读、写、NOP、激活、自刷新配置、预充电以及各ROW/BANK的激活改变等动作,较适合DDR入门使用(Including the ddr_sdr_conf_pkg.vhd, reset.vhd, ddr_dcm.vhd, user_if.vhd, ddr_sdram.vhd, Mt46v16m16.vhd and simulation TB files; designed with Virtex ii series chips, DDR_SDRAM model for the Mt46v16m16, can be used for initial control of DDR control ; Through careful understanding and logic control, in-depth understanding of DDR chip internal structure; Support 133MHz system clock frequency, burst length of 2, can be read, write, NOP, activation, self-refresh configuration, pre-charge and the activation of the ROW / BANK change action, more suitable for DDR entry)
Platform: | Size: 20480 | Author: 唛侬 | Hits:

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