Search - C to Verilog

Search - C to Verilog - List

[Other] CLOCK_co-design_of_C_and_Verilog DL : 0: A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation results. A co-design example of C and Verilog.
Update : 2008-10-13 Size : 36.91kb Publisher : Annbb
[Other] Find_medium_value_co-design_of_C_and_Verilog DL : 0: A code writing by Verilog which can find medium value. With a C file to see the simulation results. A co-design example of C and Verilog.
Update : 2008-10-13 Size : 10.77kb Publisher : Annbb
[Other] RGB_color_transform_gray_level_co-design_of_C_and_ DL : 0: to use verilog code and c to translate a RGB bmp image(512*512) to a gray level image
Update : 2008-10-13 Size : 530.63kb Publisher : Annbb
[Embeded-SCM Develop] BIN2BCD DL : 0: 10进制to BCD转换算法-Decimal to BCD conversion algorithm
Update : 2025-02-17 Size : 1kb Publisher : 好
[VHDL-FPGA-Verilog] Verilog2C++ DL : 0: 将Verilog代码转换成C++代码的软件，C源代码。-soft for changing Verilog code to c++ code ,c code
Update : 2025-02-17 Size : 41kb Publisher : kata
[VHDL-FPGA-Verilog] LDOTESTSYSTEM DL : 0: 这是一个GPIB源程序代码,里面有硬件相对应的代码-This is a GPIB source code, which corresponds to a hardware code
Update : 2025-02-17 Size : 82kb Publisher : 李成有
[Crack Hack] rsa-cpp DL : 0: RSA加密C源码 1978年就出现了这种算法，它是第一个既能用于数据加密也能用于数字签名的算法。它易于理解和操作，也很流行。算法的名字以发明者的名字命名：Ron Rivest, AdiShamir 和 Leonard Adleman。但RSA的安全性一直未能得到理论上的证明。-RSA encryption C source code 1978 on the emergence of this algorithm, it is the first not only for data encryption can be used for digital signature algorithms. It is easy to understand and operate, but also very popular. Algorithm
Update : 2025-02-17 Size : 5kb Publisher : zen
[Algorithm] fft-C DL : 0: 采用C语言设计的FFT代码，在C语言下调试通过。文件为word文档，需要嵌入到自己的程序中-Using C language designed FFT code in C language under the debugger through. Document for the word document, the need to embed into their own procedures
Update : 2025-02-17 Size : 3kb Publisher : 李文良
[Other] CLOCK_co-design_of_C_and_Verilog DL : 0: A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation results. A co-design example of C and Verilog.
Update : 2025-02-17 Size : 37kb Publisher : Annbb
[Other] RGB_color_transform_gray_level_co-design_of_C_and_ DL : 0: to use verilog code and c to translate a RGB bmp image(512*512) to a gray level image -to use verilog code and c to translate a RGB bmp image (512* 512) to a gray level image
Update : 2025-02-17 Size : 685kb Publisher : Annbb
[VC/MFC] HandelC DL : 0: Handel-C语言的学习文档。Handel-C语言由C/C++演化而来，可以自动实现C到VHDL、C到Verilog、C到EDIF等转换。在DK环境中，DK+Handel-C工具能直接把基于C语言的设计转变为优化的HDL(可以实现：C到VHDL、C到Verilog、C到EDIF等的自动生成)，进而通过FPGA实现，从而保证了各种复杂的高难算法在工程应用的实时性。-Handel-C language documentation. Handel-C language by C/C++ Evolved, you can automatically C to VHDL, C to Verilog, C, etc. to convert Edif. In DK environment, DK+ Handel-C tools can be directly to the C language-based design into optimized HDL (can be achieved: C to VHDL, C to Verilog, C, etc. to Edif automatically generated), then through the FPGA to achieve, thus ensuring a variety of complex algorithms in difficult real-time engineering applications.
Update : 2025-02-17 Size : 1.37mb Publisher : 杜杰
[Audio program] EchoClear DL : 1: vc++源码，消除回声处理，可用于音频处理； -vc++ source code, deal with the elimination of echo can be used for audio processing
Update : 2025-02-17 Size : 896kb Publisher : toven
[.net] StopWatch DL : 0: 用C#写的跑表，用于学习Timer控件和C#下的stopwatch类，在VS.net 2005下运行通过.-Using C# to write the stopwatch for the study and Timer controls and C# under the stopwatch class, VS.net 2005 in the run through.
Update : 2025-02-17 Size : 38kb Publisher : weixin
[VHDL-FPGA-Verilog] spasion_flash_verilog_model DL : 0: verilog模型,用于仿真flash，可以快速地看懂-verilog model for flash controller specified for spasion flash, please download it look at it
Update : 2025-02-17 Size : 221kb Publisher : jiangwen
[Crack Hack] ECC DL : 0: 我整理的ECC加密算法，源码和C实现的理论指导，有这个可以做出ECC加密算法-I am finishing ECC encryption algorithm, source and C to achieve the theoretical guidance, it can make ECC encryption algorithm
Update : 2025-02-17 Size : 812kb Publisher : oliver
[Other] sc2v_latest.tar DL : 0: system C to verilog converter
Update : 2025-02-17 Size : 155kb Publisher : Viki
[VHDL-FPGA-Verilog] Jpeg_decoder DL : 1: It is jpeg_decoder program. Source code are C and Verilog HDL.File .c reads data from jpeg and convert it to binary bit stream.Decoder is by verilog file
Update : 2025-02-17 Size : 195kb Publisher : doulce
[VHDL-FPGA-Verilog] MIT_Video-Scaler DL : 0: MIT的video scaler论文，文章后面附有c和verilog程序源代码，分为水平缩放和垂直缩放-MIT video scaler papers, articles, source code attached to the back, divided into horizontal scaling and vertical scaling
Update : 2025-02-17 Size : 6.61mb Publisher : zz
[Other] 5-HandelC DL : 0: Handel-C语言的学习文档。Handel-C语言由C/C++演化而来，可以自动实现C到VHDL、C到Verilog、C到EDIF等转换。在DK环境中，DK+Handel-C工具能直接把基于C语言的设计转变为优化的HDL(可以实现：C到VHDL、C到Verilog、C到EDIF等的自动生成)，进而通过FPGA实现，从而保证了各种复杂的高难算法在工程应用的实时性。(Handel-C language documentation. Handel-C language by C/C++ Evolved, you can automatically C to VHDL, C to Verilog, C, etc. to convert Edif. In DK environment, DK+ Handel-C tools can be directly to the C language-based design into optimized HDL (can be achieved: C to VHDL, C to Verilog, C, etc. to Edif automatically generated), then through the FPGA to achieve, thus ensuring a variety of complex algorithms in difficult real-time engineering applications.)
Update : 2025-02-17 Size : 1013kb Publisher : 艾斯德斯
[Other] Verilog codes DL : 0: IT IS A CARRY S ELECT ADDER TO IMPROVE PERFORMANCE.
Update : 2025-02-17 Size : 3kb Publisher : JackRIDGE

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