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Description: 没办法才上传的;有用的没多少大家别介意我qq94229631有事联系-can not only upload; There is little useful we Biegeyi I qq94229631 emergency contact
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Size: 1033216 |
Author: 曹延安 |
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Description: 无沦是用离散逻辑、可编程逻辑,还是用全定制硅器件实现的任何数字设计,为了成功地操
作,可靠的时钟是非常关键的。设计不良的时钟在极限的温度、电压或制造工艺的偏差情况下将
导致错误的行为,并且调试困难、花销很大。 在设计PLD/FPGA时通常采用几种时钟类型。时钟可
分为如下四种类型:全局时钟、门控时钟、多级逻辑时钟和波动式时钟。多时钟系统能够包括上
述四种时钟类型的任意组合。-without the expense of discrete logic, programmable logic, or a full-custom silicon device of any digital design, in order to successfully operate, reliable clock is very critical. The poor design of the clock, the limits of temperature, voltage or manufacturing process of the deviation would lead to wrong behavior, and debugging difficulties, costing much. The design PLD/FPGA usually use several types clock. The clock can be divided into the following four types : global clock, clock gating, multi-level logic clock and volatility clock. Multi-clock system to include the above four types of arbitrary clock portfolio.
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Size: 402432 |
Author: 与言 |
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Description: 基于FPGA的CAN总线控制器,VERILOGHDL源代码,Q2仿真实现。可用。-FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.
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Size: 38912 |
Author: wl |
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Description: 基于FPGA的can 总线设计,采用verilog语言编写。在FPGA的开发环境下,新建一个工程,然后将本文件中的各个源代码添加进工程里,即可运行仿真。-FPGA-based bus design can use verilog language. FPGA development environment, a new project, and then the paper all the source code to add the project, Simulation can be run.
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Size: 862208 |
Author: 李浩 |
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Description: < FPGA数字电子系统设计与开发实例导航> 一书的代码,FPGA数字电子系统设计与开发实例导航,用硬件描述语言编写的,I2C,UART,USB,VGA,CAN-BUS,网络等等的书籍配套原代码。。。。
使用方法:
1.拷贝到硬盘。
2.用ISE创建项目,分别加入各个代码文件,即可。-<FPGA digital electronic systems design and development examples of navigation> a book code, FPGA digital electronic systems design and development examples of navigation, using hardware description languages, I2C, UART, USB, VGA, CAN-BUS, network books, etc. matching the original code. . . . Usage: 1. Copy to your hard disk. 2. With ISE to create the project, respectively, to the various code files, you can.
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Size: 1567744 |
Author: 卢桂荣 |
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Description: FPGA-CPLD_DesignTool(example5-6),需要的朋友可以下载-FPGA-CPLD_DesignTool (example5-6), a friend in need can be downloaded
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Size: 377856 |
Author: 磊 |
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Description:
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Size: 865280 |
Author: 刘立 |
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Description: Verilog实现的DDS正弦信号发生器和测频测相模块,DDS模块可产生两路频率和相位差均可预置调整的值正弦波,频率范围为20Hz-5MHz,相位范围为0°-359°,测量的数据通过引脚传输给单片机,单片机进行计算和显示。-Verilog realize the DDS sine wave signal generator and frequency measurement module test phase, DDS module can generate both frequency and phase difference can be preset to adjust the value of sine wave, frequency range of 20Hz-5MHz, phase range of 0 °-359 ° , measurement data and transmit them to the single-chip pin, single-chip microcomputer to calculate and display.
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Size: 1371136 |
Author: haoren |
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Description: 自己设计的Smartcard功能模块,已经通过vcs仿真和FPGA验证,可以使用。-Smartcard functionality of their own design module, has passed vcs simulation and FPGA verification, you can use.
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Size: 16384 |
Author: 君懿 |
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Description: 用fpga实现的DA转换器,有说明和源码,VDHL文件。
A PLD Based Delta-Sigma DAC
Delta-Sigma modulation is the simple, yet powerful,
technique responsible for the extraordinary
performance and low cost of today s audio CD
players. The simplest Delta-Sigma DAC consists of a
Delta-Sigma modulator and a one bit DAC. Since,
both of these components can be realized using
digital circuits, it is possible to implement a low
precision Delta-Sigma DAC using a PLD.-Using FPGA to achieve the DA converter, has descriptions and source code, VDHL document. A PLD Based Delta-Sigma DACDelta-Sigma modulation is the simple, yet powerful, technique responsible for the extraordinaryperformance and low cost of today s audio CDplayers. The simplest Delta-Sigma DAC consists of aDelta-Sigma modulator and a one bit DAC. Since , both of these components can be realized usingdigital circuits, it is possible to implement a lowprecision Delta-Sigma DAC using a PLD.
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Size: 58368 |
Author: 开心 |
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Description: FPGA控制VGA接口显示汉字!VHDL源码!喜欢的朋友可以看看!-FPGA control interface VGA display Chinese characters! VHDL source! Favorite friends can see!
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Size: 2048 |
Author: 陈谦 |
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Description: 这些课件可以作为对FPGA有兴趣的人学习的入门资料,包含EDA的概述、FPGA结构与配置、VHDL语言、QuartusII软件、SOPC和NIosII嵌入式处理器设计、DSP Builder系统设计工具等内容-These courseware on the FPGA can be used as those who are interested in learning introductory information, including EDA overview, FPGA structure and configuration, VHDL language, QuartusII software, SOPC and NIosII embedded processor design, DSP Builder tools for system design, etc.
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Size: 25555968 |
Author: wangxujun |
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Description: can IP CORE .VERY GOOD AS A STUDY FILE-can IP CORE. VERY GOOD AS A STUDY FILE
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Size: 98304 |
Author: lijun |
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Description: 基于FPGA的LCD1602显示,可根据实际内容修改显示内容-FPGA-based LCD1602 display can be modified according to the actual contents of display content
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Size: 489472 |
Author: 冀少威 |
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Description: FPGA驱动LCD12864显示,可显示图形和文字,显示内容可根据实际情况而定-FPGA-driven LCD12864 show that can display graphics and text, display content can be determined according to the actual situation
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Size: 990208 |
Author: 冀少威 |
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Description: 基于FPGA的VGA接口显示程序,可显示三种彩色条纹-FPGA-based interface VGA display program can display the three color stripes
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Size: 464896 |
Author: 冀少威 |
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Description: 这样就可以在FPGA内实现双口RAM了-This can be achieved in the FPGA dual-port RAM
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Size: 4096 |
Author: zhan |
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Description: 收集了目前关于FPGA设计的论坛,大家如果有什么疑问,可以到这些论坛上求助。-The collection of the current design of the forum on the FPGA, there is little doubt if the U.S. can go to for help on these forums.
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Size: 13312 |
Author: 张芸 |
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Description: 1) 主芯片:Altera 的FLEX10K20TC144-4 STC89C58RD+。
2) 要求扩展键盘接口电路,可以实现电子琴的一般功能,进行乐曲的手动演奏,此外还应该具有存储功能,可以将演奏的乐曲进行存储并在人工控制下进行回放。
3) 完成系统方案设计。
4) 编制相应的VHDL程序并进行相应的仿真工作,完成系统的调试工作。
5) 编写51系统程序,完成初始化、系统控制等功能。
6) 利用51系统实现系统的在线配置。
7) 发挥部分
可以进行乐曲的自动演奏。
-1) Main chipset: Altera' s FLEX10K20TC144-4 STC89C58RD+. 2) require the expansion of the keyboard interface circuit can be achieved general organ function, to music performed manually, in addition should have a storage function, which will perform the music store and playback under manual control. 3) complete the system design. 4) the preparation of the corresponding procedures and the corresponding VHDL simulation work, the completion of system testing. 5) procedures for the preparation of 51 systems to complete the initialization, the system control functions. 6) the use of 51 on-line system configuration. 7) to play some music can be performed automatically.
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Size: 68608 |
Author: 任大志 |
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Description: FPGA控制SJA1000实现CAN协议 适合深入学子FPGA的学生 很不错-FPGA control the SJA1000 CAN protocol for in-depth realization of the students are very good students FPGA
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Size: 17577984 |
Author: qzl001 |
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