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[Post-TeleCom sofeware systems] FPGAimplementationforCDMAsystem

Description: CDMA数字基带收发系统发送部分的FPGA设计与仿真-CDMA digital base-band transceiver system to send part of the FPGA design and simulation
Platform: | Size: 103424 | Author: Duncan | Hits:

[Communication] sfs

Description: DW 256 DUP(?) STACK1 ENDS DDATA SEGMENT MES1 DB The least number is:$ MES2 DB 0AH,0DH, The largest number is:$ NUMB DB 0D9H,07H,8BH,0C5H,0EBH,04H,9DH,0F9H DDATA ENDS CODE SEGMENT ASSUME CS:CODE,DS:DDATA START: MOV AX,DDATA MOV DS,AX MOV SI,OFFSET NUMB MOV CX,0008H JCXZ A4 MOV BH,[SI] MOV BL,BH A1: LODSB AL=DS:[SI],SI=SI+1 CMP AL,BH JBE A2 MOV BH,AL JMP A3 A2: CMP AL,BL JAE A3 MOV BL,AL A3: LOOP A1 A4: MOV DX,OFFSET MES1 show mes1 MOV AH,09H INT 21H MOV AL,BL show the least number AND AL,0F0H get the highest 4 bits SHR AL,4 CMP AL,0AH JB C2 ADD AL,07H C2: ADD AL,30H MOV DL,AL show character MOV AH,02H INT 21H MOV AL,BL AND AL,0FH get the lowest 4 bits CMP AL,0AH JB C3 ADD AL,07H C3: ADD AL,30H MOV DL,AL show character MOV AH,02H INT 21H MOV DX,OFFSET MES2 show mes2 MOV AH,09H INT 21H -DW 256 DUP (?) STACK1 ENDSDDATA SEGMENTMES1 DB The least number is: $ MES2 DB 0AH, 0DH, The largest number is: $ NUMB DB 0D9H, 07H, 8BH, 0C5H, 0EBH, 04H, 9DH, 0F9HDDATA ENDSCODE SEGMENT ASSUME CS: CODE, DS: DDATASTART: MOV AX, DDATA MOV DS, AX MOV SI, OFFSET NUMB MOV CX, 0008H JCXZ A4 MOV BH, [SI] MOV BL, BHA1: LODSB AL = DS: [SI], SI = SI+ 1 CMP AL, BH JBE A2 MOV BH, AL JMP A3A2: CMP AL, BL JAE A3 MOV BL, ALA3: LOOP A1A4: MOV DX, OFFSET MES1 show mes1 MOV AH, 09H INT 21H MOV AL, BL show the least number AND AL , 0F0H get the highest 4 bits SHR AL, 4 CMP AL, 0AH JB C2 ADD AL, 07H C2: ADD AL, 30H MOV DL, AL show character MOV AH, 02H INT 21H MOV AL, BL AND AL, 0FH get the lowest 4 bits CMP AL, 0AH JB C3 ADD AL, 07HC3: ADD AL, 30H MOV DL, AL show character MOV AH, 02H INT 21H MOV DX, OFFSET MES2 show mes2 MOV AH, 09H INT 21H
Platform: | Size: 1024 | Author: 张于 | Hits:

[Driver Develop] CDMA1

Description: 关于CDMA的工程设计手册，人民邮电版本-About CDMA engineering design manual version of Posts And Telecommunications News
Platform: | Size: 2579456 | Author: | Hits:

[GPS develop] rng

Description: 通信系统中的噪声发生器，可用于ＣＤＭＡ信号源电路。-Communication system noise generator can be used for CDMA signal source circuit.
Platform: | Size: 1024 | Author: Li Gengmin | Hits:

[Books] 33

Description: CDMA基带信号发生器设计与仿真.PDF-CDMA base-band signal generator design and simulation. PDF
Platform: | Size: 121856 | Author: 秦雄华 | Hits:

[matlab] CDMACoax

Description: this a mix file.in this cdma vhdl ,simulink file included-this is a mix file.in this cdma vhdl ,simulink file included
Platform: | Size: 54272 | Author: amisha | Hits:

[VHDL-FPGA-Verilog] WIRELESS

Description: This file contains source code for DS-CDMA transciver using VHDL. it is having two source codes one is for Transmitter and another is for reciever programme.
Platform: | Size: 4096 | Author: RUPA KRISHNA | Hits:

[VHDL-FPGA-Verilog] AMBA

Description: AMBA总线结构的VHDL代码 AMBA总线VHDL代码范例-AMBA BUS example
Platform: | Size: 6144 | Author: Yan Sun | Hits:

[Other] Fuzzy_Logic_Based_Call_Admission

Description: Capacity of CDMA system depends on an interference level in the system. There are therefore RRM (Radio Resources Management) functions, which are responsible for supplying optimum coverage, ensuring efficient use of physical resources and providing the maximum planned capacity. A call admission control algorithm based on load factor evaluation and a fuzzy logic based call admission control algorithm are presented and mutually compared in this contribution
Platform: | Size: 398336 | Author: raghaw | Hits:

[VHDL-FPGA-Verilog] deinterleave

Description: CDMA.1X中，解交织的FPGA实现，程序基于VHDL编写，在XILINX开发板实现。-CDMA.1X, the solution of interwoven FPGA implementation, the program prepared based on VHDL, in the XILINX development board to achieve.
Platform: | Size: 268288 | Author: 蔡蔡 | Hits:

[Software Engineering] RAKE_FPGA

Description: RAKE技术与CDMA系统相结合，能够带来系统容量和通信质量的极大提 高。根据军事通信中对设备便携性及低功耗的特殊要求，本文研究了一种便携式 基站的收发系统，重点研究了其中的RAKE接收部分。给出了系统的发送方案和 接收方案，对接收机部分所涉及的关键技术和算法，包括数字下变频技术、匹配相关技术、多径搜索技术、信道估计技术、解调及多径合并技术进行了较为详细的分析和说明。在此基础上，运用VHDL语言进行了硬件平台上FPGA部分的功能实现，并对整个系统进行了调试，给出了一些相关的仿真及测试结果。最后对该系统还需进一步研究的问题进行了简要的介绍，对调试过程中的出现的一些问题进行了简单的分析和小结。 -CDMA system with RAKE combining technology, can bring the system capacity and communication quality significantly raised High. According to military communications equipment portability and low power consumption special requirements, this paper, a portable The base station transceiver system, which focuses on the RAKE receiving part. Then the system sends the program and Receiving scheme, the receiver part of the key technologies involved and algorithms, including digital down-conversion technology, matching the relevant technology, multi-path search and channel estimation, demodulation and multi-path merging techniques on a more detailed analysis and explanation. On this basis, the use of VHDL, FPGA hardware platform to achieve some functionality, and debugging the system, given some of the relevant simulation and test results. Finally the system need further study are briefly introduced, and the emergence of the process of debugging some problems in a simple analysis and summar
Platform: | Size: 2499584 | Author: 徐进 | Hits:

[VHDL-FPGA-Verilog] CDMA_MULT3_ise9migration

Description: CDMA Source code and documentation
Platform: | Size: 453632 | Author: hr | Hits:

[VHDL-FPGA-Verilog] CDMA

Description: CDMA source code and documentation best code
Platform: | Size: 4096 | Author: hr | Hits:

[assembly language] syn_clk

Description: 基于VHDL语言的CDMA基带传输系统设计实现传输-VHDL
Platform: | Size: 1024 | Author: 韦文安 | Hits:

[assembly language] delaymwal

Description: 00基于VHDL语言的CDMA基带传输系统源代码-VHDL
Platform: | Size: 1024 | Author: 韦文安 | Hits:

[VHDL-FPGA-Verilog] cdma

Description: vhdl code for flip-flop,lfsr
Platform: | Size: 104448 | Author: sandeep | Hits:

[VHDL-FPGA-Verilog] bpsk_spread_spectrum_modulator_demodulator

Description: code for bpsk spread spectrum modulator used in cdma -code for bpsk spread spectrum modulator used in cdma ..
Platform: | Size: 8192 | Author: ANIL | Hits:

[VHDL-FPGA-Verilog] cdma

Description: 使用verilog在QII系统中开发的一个简单的4用户CDMA系统。-In QII system using verilog developed a simple four-user CDMA system.
Platform: | Size: 4254720 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilog] CDMA_DECODING

Description: CDMA encoding using VHDL
Platform: | Size: 10240 | Author: muruga | Hits:

[source in ebook] CDMA_ver

Description: Iplementation of CDMA reciever and Transmitter using VHDL and Verilog Coding
Platform: | Size: 4096 | Author: Fardeen | Hits:

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