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[Other] CIC滤波器的补偿 DL : 0: CIC滤波器的补偿，适用于抽取内插滤波器的设计
Update : 2010-01-06 Size : 1.98kb Publisher : lwy_xd@163.com
[RFID] cic code Verilog代码 DL : 0: cic code选用verilog代码编写
Update : 2011-05-19 Size : 2.57kb Publisher : flcan@163.com
[VHDL-FPGA-Verilog] CIC DL : 0: 介绍了积分梳状滤波器(CIC)设计，压缩包里面有程序的流程图，采用verilogHDL编写，在modelsim上可以实现仿真结果，非常不错-Introduced the integral comb filter (CIC) design, there are procedures for compressed packets flow chart, using verilogHDL prepared on the ModelSim simulation results can be achieved very good
Update : 2025-02-17 Size : 150kb Publisher : yaoyongshi
[Other] cic DL : 0: hogenauer cic滤波器的算法的研究及其与在fpga中的实现，简明易懂。-hogenauer cic filter algorithm and its relationship to the FPGA in the realization of easy to understand.
Update : 2025-02-17 Size : 251kb Publisher : 岑楠
[VHDL-FPGA-Verilog] cic DL : 0: verilog码写的CIC滤波器的程序，包括4倍抽取CIC滤波器和内插的CIC滤波器两个-Verilog code written by CIC filter procedures, including 4 times the extraction CIC filter and the CIC interpolation filter two
Update : 2025-02-17 Size : 22kb Publisher : 桃子
[Embeded-SCM Develop] CIC DL : 0: 本文讲解CIC数字滤波器的设计,对设计者有很大的帮助-This article on the CIC digital filter design, for designers of great help
Update : 2025-02-17 Size : 126kb Publisher : asdtgg
[Communication-Mobile] CIC DL : 0: CIC梳妆滤波器生成器，生成任意位数任意长度的CIC滤波器源代码-Dressing CIC filter generator to generate any arbitrary length of the median of the CIC filter source code
Update : 2025-02-17 Size : 131kb Publisher : lizhizhou
[VHDL-FPGA-Verilog] CIC DL : 0: 台湾国家晶元设计中心VHDL内部培训资料(CIC).pdf-Taiwan
Update : 2025-02-17 Size : 2.85mb Publisher : 张贺寅
[VHDL-FPGA-Verilog] CIC DL : 0: cpld/fpga积分梳状滤波器(CIC)设计-cpld/fpga Integral comb filter (CIC) design
Update : 2025-02-17 Size : 1kb Publisher : 陈臣
[matlab] cic DL : 1: 五阶CIC梳状积分滤波器，可以综合，非常有参考价值-Fifth-order CIC points comb filter, can be integrated and very useful
Update : 2025-02-17 Size : 743kb Publisher : shirley
[Software Engineering] CIC-cosinefilter DL : 0: CIC滤波器和COSine滤波器级联，改进了CIC的矛盾。英文文章-CIC filter and filter cascade CoSine improved CIC contradiction. English articles
Update : 2025-02-17 Size : 212kb Publisher : 中山太乙
[Software Engineering] CIC DL : 0: 详细介绍了cic设计需要注意的问题，对cic的设计会起到非常大的作用-CIC design details need to pay attention to the CIC design will play a very big role
Update : 2025-02-17 Size : 142kb Publisher : xiebin
[matlab] CIC DL : 0: 关于一个滤波器的程序，三级CIC抽取的源程序。-On a filter process, the three-tier CIC samples of the source.
Update : 2025-02-17 Size : 1kb Publisher : 王建龙
[matlab] CIC DL : 0: matlab实现一个decimation为4的CIC滤波器-matlab implementation of a decimation filter for 4 of the CIC
Update : 2025-02-17 Size : 1kb Publisher : morang
[matlab] cic DL : 2: 当前工程上广泛采用了一种高效滤波器，即CIC（cascaded integrator-comb filter）将其作为第一级来实现抽取、低通滤波。第二级再用一个普通的FIR滤波器就实现使后端设备工作在较低的频率下且硬件花销少、功耗也很低。-Widely used in the current project, a highly efficient filter, that is, CIC (cascaded integrator-comb filter) as the first level to achieve the extraction, low-pass filter. An ordinary second-class and then the realization of the FIR filter so that the work of the back-end equipment at a lower frequency and spending less hardware, power consumption is very low.
Update : 2025-02-17 Size : 62kb Publisher : 王奎
[Communication-Mobile] CIC DL : 0: CIC梳状滤波器verilog源码，包括积分器，下抽级以及梳状滤波器三个部分。-CIC comb filter verilog source code, including the integrator, under the pump, as well as comb filter class is in three parts.
Update : 2025-02-17 Size : 1kb Publisher : 张佳培
[VHDL-FPGA-Verilog] cic DL : 0: 在MATLAB2007A/SIMULINK环境下用DSP BUILDER8.0实现了五级CIC，解决了溢出问题。生成了可用的VHDL文件。- DSP BUILDER8.0 A 5 stages CIC filer is realized in MATLAB2007A/SIMULINK by using DSP Builder 8.0.The overflow problem is resulved.Useful VHDL files are generated at last.
Update : 2025-02-17 Size : 1.47mb Publisher : hcq
[Embeded-SCM Develop] CIC DL : 0: 积分梳妆滤波，介绍了积分梳状滤波器(CIC)设计，压缩包里面有程序的流程图，采用verilogHDL编写-jifenshuzhuanglubo
Update : 2025-02-17 Size : 151kb Publisher : zhangyunfei
[VHDL-FPGA-Verilog] CIC DL : 0: CIC IP core实现结构中自动生成的接口代码,基于软件无线电的应用，在毕业论文中已使用过。-CIC IP core to achieve the structure of the interface code automatically generated, based on software radio applications, has been used in the thesis.
Update : 2025-02-17 Size : 7kb Publisher : 黄顺涛
[VHDL-FPGA-Verilog] CIC DL : 0: 五阶CIC滤波器，用于降低数据传输速率。数字下变频技术不仅是软件无线电核心技术之一，还是中频数字化接收系统重要组成部分。数字下变频技术中广泛用到级联积分梳状滤波器（CIC滤波器）-CIC filter
Update : 2025-02-17 Size : 1.36mb Publisher : 姚琼琼

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