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[VHDL-FPGA-Verilog] 4bits_alu

Description: 实现4位加减乘除的alu，采用超前进位加法和布斯乘法，代码较为简单。-achieve four of the ALU arithmetic using CLA Bush and multiplication, code more simple.
Platform: | Size: 262144 | Author: 陈晓炜 | Hits:

[VHDL-FPGA-Verilog] adder_ahead8bit

Description: 本文件提供了用verilog HDL语言实现的8位超前进位加法器,充分说明了超前进位加法器和普通加法器之间的区别.-using verilog HDL achieve the eight-ahead adder, fully demonstrates the CLA for ordinary Adder and the distinction between.
Platform: | Size: 10240 | Author: 剑指眉梢 | Hits:

[MPI] CLA

Description: 超前进位加法器得VHDL实现小点资料代码-CLA was a small point of information VHDL code
Platform: | Size: 1024 | Author: long | Hits:

[MPI] adder

Description: 8位超前进位加法器就是使各位的进位直接由加数和被加数来决定，而不需要依赖低位进位-8-bit CLA is to make your binary direct summand by summand and to decide, rather than to rely on low binary
Platform: | Size: 7168 | Author: | Hits:

[VHDL-FPGA-Verilog] trueif

Description: 一个超前进位加法器（及其testbench) .v文件-A CLA (and its testbench). V file
Platform: | Size: 1024 | Author: QU YIFAN | Hits:

[VHDL-FPGA-Verilog] adder_32

Description: 超前进位加法器是通常数字设计所必备的，本程序为32位超前进位加法器-CLA is usually necessary for digital design, the procedure for 32-bit CLA
Platform: | Size: 1024 | Author: zhaohongliang | Hits:

[VHDL-FPGA-Verilog] 16bitCLA

Description: 基于Verilog HDL的16位超前进位加法器分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules
Platform: | Size: 7168 | Author: 韩伟 | Hits:

[MPI] adder

Description: 运用VHDL语言实现四位超前进位加法器。-VHDL language using the four CLA.
Platform: | Size: 4096 | Author: 吴伟 | Hits:

[VHDL-FPGA-Verilog] CLA.VHDL.CODE

Description: cla vhdl code with a picture files.
Platform: | Size: 339968 | Author: YD | Hits:

[VHDL-FPGA-Verilog] ADDER(2)

Description: simple 16-bet CLA adder
Platform: | Size: 2048 | Author: calvin | Hits:

[Windows Develop] adder

Description: 8位cla，采用for结构，可以扩张成32位或者16位-8 cla, used for the structure, you can expand into a 32-bit or 16-bit
Platform: | Size: 36864 | Author: sigma | Hits:

[VHDL-FPGA-Verilog] 4

Description: simple code based on verilog shifter , cla ,clg , ALU , PC
Platform: | Size: 3072 | Author: Tera | Hits:

[Other] cla

Description: a cla coding in verilog
Platform: | Size: 229376 | Author: Lee Jonggun | Hits:

[VHDL-FPGA-Verilog] 16bit-CLA

Description: 16 bit carry look ahead adder verilog code
Platform: | Size: 8192 | Author: praveen | Hits:

[VHDL-FPGA-Verilog] cla-adder

Description: cla adder code in vhdl
Platform: | Size: 8192 | Author: nirjhar | Hits:

[ARM-PowerPC-ColdFire-MIPS] CLA-CCSv3.3

Description: F28035的DSP，CCS3.3应用环境的配置，可以在一台电脑上同时打开主CPU和CLA的调试界面，对于使用CLA的并且不习惯使用新版ccs4开发环境的用户很有用！-F28035 the DSP, CCS3.3 application environment configuration on a computer at the same time open the main CPU and CLA debug interface, users not accustomed to using new version of ccs4 development environment for the use of CLA and useful!
Platform: | Size: 2850816 | Author: 徐贺 | Hits:

[Other] CLA

Description: CLA adder:use vhdl to write the carry-lookahead adder which is a type of adder used in digital logic-CLA adder
Platform: | Size: 1024 | Author: awen | Hits:

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[VHDL-FPGA-Verilog] 4bits_alu

[VHDL-FPGA-Verilog] adder_ahead8bit

[MPI] CLA

[MPI] adder

[VHDL-FPGA-Verilog] trueif

[VHDL-FPGA-Verilog] adder_32

[VHDL-FPGA-Verilog] 16bitCLA

[MPI] adder

[VHDL-FPGA-Verilog] CLA.VHDL.CODE

[VHDL-FPGA-Verilog] ADDER(2)

[Windows Develop] adder

[VHDL-FPGA-Verilog] 4

[Other] cla

[VHDL-FPGA-Verilog] 16bit-CLA

[VHDL-FPGA-Verilog] cla-adder

[ARM-PowerPC-ColdFire-MIPS] CLA-CCSv3.3

[ARM-PowerPC-ColdFire-MIPS] CLA-CCSv4.x

[assembly language] 32-bit-cla-adder

[Industry research] Memetic-CLA-PSO

[Other] CLA

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