Search - CNT10 VHDL

[Editor] cnt10

Description: 用VHDL语言编的带有异步清零功能的十进制计数器-using VHDL addendum to the asynchronous reset function with the decimal counter
Platform: | Size: 30560 | Author: yanyuntao | Hits:

[Other resource] cnt10

Description: 基于vhdl的10进制计数器模块，实现0-9计数
Platform: | Size: 24101 | Author: 贝凯 | Hits:

[Other resource] cnt10

Description: 10进制计数器，VHDL描述的，实验必备
Platform: | Size: 45923 | Author: li | Hits:

[Editor] cnt10

Description: 用VHDL语言编的带有异步清零功能的十进制计数器-using VHDL addendum to the asynchronous reset function with the decimal counter
Platform: | Size: 30720 | Author: yanyuntao | Hits:

[VHDL-FPGA-Verilog] cnt10

Description: 基于vhdl的10进制计数器模块，实现0-9计数-VHDL-based 10-band counter module, to achieve 0-9 count
Platform: | Size: 23552 | Author: 贝凯 | Hits:

Description: 本程序实现了一个数字频率计。它由一个测频控制信号发生器TESTCTL，8个有时钟的十进制计数器CNT10，一个32位锁存器REG32B组成。-This procedure implements a digital frequency meter. It consists of a frequency control signal generator TESTCTL, 8 which have the metric system clock counter CNT10, a 32-bit latch REG32B component.
Platform: | Size: 1024 | Author: liushenshen | Hits:

[VHDL-FPGA-Verilog] cnt10

Description: 10进制计数器，VHDL描述的，实验必备-10 hexadecimal counters, VHDL description of the experiment must
Platform: | Size: 46080 | Author: li | Hits:

[VHDL-FPGA-Verilog] pinluji

Description: 四位十进制频率计设计包含测频控制器（TESTCTL），4位锁存器(REG4B)，十进制计数器（CNT10）的原程序(vhd)，波形文件(wmf ),包装后的元件(bsf)。顶层原理图文件（Block1.bdf）和波形。 -Four decimal frequency meter measuring frequency controller design includes (TESTCTL), 4 bit latch (REG4B), decimal counter (CNT10) of the original procedure (vhd), waveform file (wmf), packaged components (bsf). Top-level schematic document (Block1.bdf) and waveform.
Platform: | Size: 11264 | Author: 深空 | Hits:

[VHDL-FPGA-Verilog] cnt10

Description: vhdl 十进制加法计数器设计已经调试成功-decimal adder vhdl counter the success of design debugging
Platform: | Size: 27648 | Author: 程诗宇 | Hits:

[VHDL-FPGA-Verilog] cnt10

Description: 一个用VHDL语言编写的十进制计数器，后续还有分频器、数据选择器、七段数码显示程序等软件平台是Quartus II 7.2 ，最后通过这些小的模块可以组合起来制作出一个时钟或者其它的任意进制计数器，适合初学者，通过这些程序，刚接触VHDL的学习者可以一步步的去认识和了解VHDL，最后通过设计一个具有实用功能的电路，来增加学习者的成就感和学习兴趣。所有程序软硬件调试都成功通过，硬件平台是自己学校设计的一块开发板，要了解的可以联系本人。联系QQ：782649157 -VHDL language using a decimal counter, follow-up there is divider, data selector, seven-segment digital display procedures, the software platform is Quartus II 7.2, the final adoption of these small modules can be combined to produce a clock or other arbitrary binary counter, suitable for beginners, through these procedures, new to VHDL learners can be a step by step to the awareness and understanding of VHDL, the last through the design of a practical function of the circuit, to increase the learner' s sense of achievement and interest in learning. All programs have successfully passed the hardware and software debugging, hardware platform is designed by a development of their own school board, it is necessary to know can contact me. Contact QQ: 782649157
Platform: | Size: 242688 | Author: QQ | Hits:

[VHDL-FPGA-Verilog] cnt10

Description: 超好用的十进制计数器，万能型，随时可用，好用好用好用，VHDL经典例子-perfect counter10，very very good，can be used everyehere，classical example
Platform: | Size: 1024 | Author: 李刚 | Hits:

[VHDL-FPGA-Verilog] cnt10

Description: 用八段数码管管显示十进制数，使用的是VHDL语言-Eight out of digital tube display with a decimal number, using the VHDL language
Platform: | Size: 41984 | Author: 杨云乔 | Hits:

[VHDL-FPGA-Verilog] cnt10

Description: 这是一个使用vhdl语言编写的fpga代码，它能够实现0-9之内的计数功能。-This is a use of the VHDL language fpga code, it can achieve the 0-9 count.
Platform: | Size: 1595392 | Author: yubaoming | Hits:

[Other] cnt10

Description: 基于vhdl的十进制计数器的设计，有计数的功能，是最基础的vhdl模块- Decimal
Platform: | Size: 1024 | Author: 西城 | Hits:

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[VHDL-FPGA-Verilog] CNT10

[VHDL-FPGA-Verilog] CNT10

[VHDL-FPGA-Verilog] CNT10

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