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[Other resource] counter10

Description: 该程序实现的是10进制的计数器，具有置位复位的功能。-the program is the band of 10 counters, with the home-reset function.
Platform: | Size: 13298 | Author: 许嘉璐 | Hits:

[VHDL-FPGA-Verilog] counter10

Description: 该程序实现的是10进制的计数器，具有置位复位的功能。-the program is the band of 10 counters, with the home-reset function.
Platform: | Size: 13312 | Author: 许嘉璐 | Hits:

[VHDL-FPGA-Verilog] counter10

Description: 带LDN的的同步的预置数端子，并且带CLR的异步清零端-LDN synchronization with the preset number of terminals, and cleared with CLR Asynchronous client
Platform: | Size: 1024 | Author: dws | Hits:

[Other] counter10

Description: 十进制计数器，共四位，最大计数可以达到-Decimal counter, a total of four, the largest count of 9999 can be achieved
Platform: | Size: 215040 | Author: xk | Hits:

[VHDL-FPGA-Verilog] counter10

Description: 这是一个十进制的计数器哦，是用vhdl语言开发出来的 是一个不错的十进制计数器-This is a decimal counter Oh, is vhdl language developed is a good decimal counter
Platform: | Size: 28672 | Author: 朱迁虎 | Hits:

[VHDL-FPGA-Verilog] counter10

Description: 基于VHDL语言的十进制计数器设计，8 路抢答器控制系统； EDA； CPLD； VHDL； 仿真-VHDL language based on the decimal counter design, 8-way Responder control system EDA CPLD VHDL Simulation
Platform: | Size: 178176 | Author: damon | Hits:

[VHDL-FPGA-Verilog] cnt10

Description: 超好用的十进制计数器，万能型，随时可用，好用好用好用，VHDL经典例子-perfect counter10，very very good，can be used everyehere，classical example
Platform: | Size: 1024 | Author: 李刚 | Hits:

[VHDL-FPGA-Verilog] COUNTER10

Description: 基于sopcbuilder和niosii的计数器-Based on the counter sopcbuilder and niosii
Platform: | Size: 1294336 | Author: 晨暹 | Hits:

[VHDL-FPGA-Verilog] Counter10

Description: 在quartus 9.1软件上用verilog语言编写的10进制计数器程序-The Verilog language quartus 9.1 software 10 binary counter program
Platform: | Size: 315392 | Author: 黄灼泉 | Hits:

[VHDL-FPGA-Verilog] counter10

Description: verilog编写的10进制计数器，并且功能仿真正确。软件为quartus II 11.0,和Modelsim-verilog prepared 10 binary counter, and functional simulation is correct. Software quartus II 11.0, and Modelsim
Platform: | Size: 128000 | Author: 任留阳 | Hits:

[VHDL-FPGA-Verilog] counter10

Description: 十进制计数器，比较简单，比较容易，希望大家不要见怪-decimal counter
Platform: | Size: 1024 | Author: hp | Hits:

[VHDL-FPGA-Verilog] counter10

Description: vhdl编写的十进制计数器，名字叫count10，已配好引脚(VHDL's decimal counter, named count10, has been matched with a pin)
Platform: | Size: 1422336 | Author: li 234 | Hits:

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