Search - CPLD RAM

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[Embeded-SCM Develop] VHDLRAM DL : 0: 介绍vhdl硬件描述语言的特点及设计思想，运用vhdl硬件描述语言实现计算机原理实验中RAM存储器的设计方法，重点描述了对传统计算机组成原理实验中移植到基于CPLD平台的思想-introduced vhdl hardware description language features and design ideas, vhdl use hardware description language computer science experiments RAM memory design, Description of key computer components of the traditional principle experiment to transplant platform based on the idea of CPLD
Update : 2008-10-13 Size : 30.18kb Publisher : 刘浏
[Embeded-SCM Develop] dualportRAM DL : 0: 双端口RAM的VHDL语言实现。完全在CPLD芯片上测试通过。可以实现对存储器读操作的同时对另外一个空间写操作-dual-port RAM VHDL. Totally CPLD chip test. Memory can be achieved right time to operate while the other was a space operation
Update : 2008-10-13 Size : 88kb Publisher : 王雪松
[Embeded-SCM Develop] cpld DL : 0: 8051工作于11.0592MHZ,RAM扩展为128KB的628128,FlashRom扩展为128KB的AT29C010A 128KB的RAM分成4个区(Bank) 地址分配为0x0000-0x7FFF 128KB的FlashRom分成8个区(Bank) 地址分配为0x8000-0xBFFF 为了使8051能访问整个128KB的RAM空间和128KB的FlashRom空间,在CPLD内建两个寄存器 RamBankReg和FlashRomBankReg用于存放高位地址
Update : 2008-10-13 Size : 2.38kb Publisher : CHENYUEHONG
[Other] a2d2 DL : 1: ad取样，经由cpld处理，存入ram 1000点并由串行的da进行还原
Update : 2008-10-13 Size : 176.65kb Publisher : 大星
[VHDL-FPGA-Verilog] vhdlprogram DL : 0: 用复杂可编程逻辑器件(CPLD)实现的数字钟控系统-with complex programmable logic devices (CPLD) with a digital clock control system
Update : 2025-02-17 Size : 5kb Publisher : 王永
[Special Effects] videofram DL : 0: 用CPLD控制图像卡进行帧存逻辑的verilog程序,用Quartus II 5.0打开-with CPLD control image frame buffer cards logical verilog procedures, Quartus II 5.0 Open
Update : 2025-02-17 Size : 1kb Publisher : 陈刚峰
[Embeded-SCM Develop] LA_USB DL : 0: Update : 2025-02-17 Size : 952kb Publisher : nicai
[Embeded-SCM Develop] VHDLRAM DL : 0: 介绍vhdl硬件描述语言的特点及设计思想，运用vhdl硬件描述语言实现计算机原理实验中RAM存储器的设计方法，重点描述了对传统计算机组成原理实验中移植到基于CPLD平台的思想-introduced vhdl hardware description language features and design ideas, vhdl use hardware description language computer science experiments RAM memory design, Description of key computer components of the traditional principle experiment to transplant platform based on the idea of CPLD
Update : 2025-02-17 Size : 30kb Publisher : 刘浏
[Embeded-SCM Develop] dualportRAM DL : 0: 双端口RAM的VHDL语言实现。完全在CPLD芯片上测试通过。可以实现对存储器读操作的同时对另外一个空间写操作-dual-port RAM VHDL. Totally CPLD chip test. Memory can be achieved right time to operate while the other was a space operation
Update : 2025-02-17 Size : 88kb Publisher : 王雪松
[Embeded-SCM Develop] cpld_fpga_sample_program DL : 0: 全是FPGA的例子对大家应该有好处大家赶快下把知识不等人-are examples we should be beneficial to everyone as soon as possible under the knowledge from people
Update : 2025-02-17 Size : 240kb Publisher : sss
[Embeded-SCM Develop] cpld DL : 0: Update : 2025-02-17 Size : 2kb Publisher : CHENYUEHONG
[VHDL-FPGA-Verilog] ram_test DL : 0: 实现cpld 外挂存储器,并实时测试内存的好坏.可嵌入到系统中-CPLD realize plug memory, and real-time test of good or bad memory. Can be embedded into the system
Update : 2025-02-17 Size : 1kb Publisher : 曾工
[Other] a2d2 DL : 0: ad取样，经由cpld处理，存入ram 1000点并由串行的da进行还原-ad sampling, by the CPLD deal, deposited by the serial ram 1000 points to restore the da
Update : 2025-02-17 Size : 176kb Publisher :
[VHDL-FPGA-Verilog] 8051-Verilog DL : 0: 使用CPLD仿真8051核,内有源程序和说明,来之不易-CPLD simulation using 8051 nuclear, which has source code and description, the hard-won
Update : 2025-02-17 Size : 88kb Publisher : 梁志洪
[Embeded-SCM Develop] usbusermanual_altera DL : 0: RAM implementation cpld
Update : 2025-02-17 Size : 127kb Publisher : NguyenViet
[VHDL-FPGA-Verilog] ram4bit DL : 0: ram 4 bit with cpld, xinix & language is vhdl.
Update : 2025-02-17 Size : 1kb Publisher : ali
[VHDL-FPGA-Verilog] PseudoHC11_MCU DL : 0: This extensive proyect turns an FPGA or CPLD into an HC11 simulation. It takes in various opcodes and performs several 8bit operations. The package includes an ALU, UART, RAM module, LCD display and 7 segments as well.-This extensive proyect turns an FPGA or CPLD into an HC11 simulation. It takes in various opcodes and performs several 8bit operations. The package includes an ALU, UART, RAM module, LCD display and 7 segments as well.
Update : 2025-02-17 Size : 12kb Publisher : mahedros87
[VHDL-FPGA-Verilog] Package DL : 0: Package consists of two pdf files: i)cdr project: theory and implementation of vhdl ii)I2C bus controller: xilinx implementation of uC interface on CPLD Package consists of 7 vhdl files: string_detector: detects the continuous string of 111 led_driver: code for running leds on dvpt board clk_div: clock divider circuitry (component for led code) mem: memory component for led code ram_dual: dual port ram implementation-Package consists of two pdf files: i)cdr project: theory and implementation of vhdl ii)I2C bus controller: xilinx implementation of uC interface on CPLD Package consists of 7 vhdl files: string_detector: detects the continuous string of 111 led_driver: code for running leds on dvpt board clk_div: clock divider circuitry (component for led code) mem: memory component for led code ram_dual: dual port ram implementation
Update : 2025-02-17 Size : 4.39mb Publisher : Sharav
[DSP program] DEC6713_krsys DL : 0: CPLD写数进RAM，从DSP读数，测试通讯-CPLD write a number into the RAM, the readings from the DSP test communications
Update : 2025-02-17 Size : 511kb Publisher : 桃李
[VHDL-FPGA-Verilog] CPLD_AD_AVR DL : 0: CPLD程序，程序中实现了PWM波的产生、ADS8364并行高速AD的读写控制，与AVR单片机的通信控制。CPLD以类似外部RAM的方式被AVR读写，AVR单片机只需要向固定的地址写入或者读取即可。本程序对高速数据采集系统有很好的参考作用，可以以此修改为其他应用场合。-The CPLD program, the program to achieve a PWM wave generation high-speed AD ADS8364 parallel read and write control, and communication control of the AVR microcontroller. CPLD manner similar to the external RAM read and write by the AVR, AVR microcontroller only needs to fixed address to write or read can. The good reference procedures for high-speed data acquisition system, can be used to modify other applications.
Update : 2025-02-17 Size : 4kb Publisher : emouse

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