Search - CPLD SPI

[Other resource] PC104-CPLD-SPI

Description: VxWorks下PC104-CAN驱动程序设计,系统的基本功能是通过CPLD 来实现PC/104 总线SPI 总线的数据交换
Platform: | Size: 142173 | Author: pangbai | Hits:

[Documents] FPGA实现SPI

Description: 串行外设接口（SPI） cpld 被动接收
Platform: | Size: 35840 | Author: gzdly@126.com | Hits:

[VHDL-FPGA-Verilog] SPI_VHDL

Description: SPI串口的内核实现（vhdl）,可以用qII等软件直接加到FPGA或者CPLD里面.-the SPI Serial Kernel (vhdl) can be used directly qII software foisted CPLD or FPGA inside.
Platform: | Size: 13312 | Author: efly | Hits:

[Embeded-SCM Develop] vspi_VHDL

Description: FPGA/CPLD VHDL语言实现SPI，拥有两种模式，FPGA/CPLD即可工作在主机模式，又可工作在从机模式 -FPGA/CPLD VHDL language SPI, have the two models, FPGA/CPLD can work in host mode, but also work in slave mode
Platform: | Size: 248832 | Author: 张焱 | Hits:

[VxWorks] PC104-CPLD-SPI

Description:
Platform: | Size: 142336 | Author: pangbai | Hits:

[Embeded-SCM Develop] vhdlthreelinespi

Description: ＳＰＩ总线与ＣＰＬＤ之间的通信程序，可实现ＳＰＩ串行输入，通过移位寄存器后并行输出-SPI bus and the CPLD communication between these procedures is to realize SPI serial input, through the shift register parallel output after
Platform: | Size: 1024 | Author: 金臻炜 | Hits:

[VHDL-FPGA-Verilog] spi_master

Description: 基于CPLD/FPGA的SPI控制的IP核的实现spi_master-Based on CPLD/FPGA to control the SPI realize the IP core spi_master
Platform: | Size: 1024 | Author: linsky | Hits:

[VHDL-FPGA-Verilog] an485_design_example

Description: AN485_CH-MAX II CPLD 中的串行外设接口主机（verilog SPI）
Platform: | Size: 312320 | Author: zhiqiang | Hits:

[Other] mcu+CPLD

Description: 嵌入式工程师必要的参考材料。mcu 和 CPLD 综合运用 ,有大量实例-Embedded engineers necessary reference material. mcu and comprehensive use of CPLD, a large number of examples
Platform: | Size: 7961600 | Author: cruise | Hits:

[SCM] mcu-cpld-spi

Description: mcu与cpld之间spi接口程序，mcu为master，cpld用verilog写成slave模块-mcu with spi interface program between the CPLD, mcu for the master, cpld written using Verilog slave module
Platform: | Size: 110592 | Author: 叶灿 | Hits:

[Embeded-SCM Develop] AIC

Description: 使用FPGA/CPLD设置语音AD、DA转换芯片AIC23，FPGA/CPLD系统时钟为24.576MHz 1、AIC系统时钟为12.288MHz，SPI时钟为6.144MHz 2、AIC处于主控模式 3、input bit length 16bit output bit length 16bit MSB first 4、帧同步在96KHz-The use of FPGA/CPLD set voice AD, DA conversion chip AIC23, FPGA/CPLD system clock for the 24.576MHz 1, AIC system clock is 12.288MHz, SPI clock is 6.144MHz 2, AIC is in master mode 3, input bit length 16bit output bit length 16bit MSB first 4, frame synchronization at 96KHz
Platform: | Size: 2048 | Author: 张键 | Hits:

[VHDL-FPGA-Verilog] slave_spi_ctrl

Description: SPI 的FPGA控制源代码，用于一般通用的SPI技术，FPGA/CPLD控制的AD数据采集-SPI control course code
Platform: | Size: 1024 | Author: luxiaogang | Hits:

[VHDL-FPGA-Verilog] spi.sim

Description: vhdl spi cpld simulation
Platform: | Size: 4096 | Author: mohamad | Hits:

[VHDL-FPGA-Verilog] spi.tan

Description: vhdl spi cpld fpga cofiguration
Platform: | Size: 6144 | Author: mohamad | Hits:

[Applications] CPLD

Description: ad采集的小模块，实现串口转并口的功能，串口是SPI的接口-ad collector modoudle ad ad ad ad ad da da da da shuzi moni moni shuzi caiji caiji caiji caiji caiji caiji caiji
Platform: | Size: 32768 | Author: ninglige | Hits:

[VHDL-FPGA-Verilog] spi

Description: 基于CPLD的用SPI控制pwm的源码，用VHDL编写，已经测试，可以直接使用
Platform: | Size: 1024 | Author: DRzhou | Hits:

[DSP program] DA

Description: 00IC2407＋CPLD板上选用的DA转换器是TI公司的TLC5620,TLC5620是串行4通道8位 DA 转换器，DSP 通过 SPI 与其接口，TLC5620 的工作频率是 1MHZ,所有 DSP 的 SPI也必须设置位1MHZ, -00IC2407+ CPLD DA converter board is selected TI' s TLC5620, TLC5620 is a serial 4-channel 8-bit DA converters, DSP and its interface, through the SPI, TLC5620 operating frequency is 1MHZ, all the DSP' s SPI must also be set bit 1MHZ,
Platform: | Size: 67584 | Author: lizhenli | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list