Search - CPLD UART

[Communication] FPGA-UART

Description: 用FPGA器件实现UART核心功能的一种方法串行外设都会用到RS232-C异步串行接口，传统上采用专用的集成电路即UART实现，如TI、EXAR、EPIC的550、452等系列，但是我们一般不需要使用完整的UART的功能，而且对于多串口的设备或需要加密通讯的场合使用UART也不是最合适的。如果设计上用到了FPGA/CPLD器件，那么就可以将所需要的UART功能集成到FPGA内部，本人最近在用XILINX的XCS30做一个设计的时候，就使用VHDL将UADT的核心功能集成了，从而使整个设计更加紧凑，更小巧、稳定、可靠
Platform: | Size: 27456 | Author: 开心 | Hits:

[Com Port] uart

Description: 采用CPLD实现串口通信（Verilog硬件描述语言）
Platform: | Size: 5106 | Author: wuzhidong | Hits:

[Windows Kernel] CPLD的串口程序（VHDL）

Description:

在CPLD上实现UART，利用VHDL进行编程。

Platform: | Size: 746970 | Author: greatlht | Hits:

[VHDL-FPGA-Verilog] sopc

Description: altera推出的基于它们fpga和cpld的构建嵌入式系统的新技术sopc的介绍。其集成在quartus II中-ALTERA due to launch them and they simply cpld Construction of the new Embedded System Technology sopc briefing. Its integrated into the Quartus II
Platform: | Size: 8863744 | Author: 刘吉 | Hits:

[VHDL-FPGA-Verilog] Altera_uart_VHDL

Description: FPGA/CPLD应用,uart通讯VHDL原码.-FPGA/CPLD applications, UART communications VHDL source.
Platform: | Size: 10240 | Author: cyberworm | Hits:

[VHDL-FPGA-Verilog] Altera_uart_Verilog

Description: FPGA/CPLD应用,uart的Verilog HDL原码-FPGA/CPLD applications, UART Verilog HDL source
Platform: | Size: 10240 | Author: cyberworm | Hits:

[Software Engineering] verilog50%

Description: 本文主要介绍了50％占空比三分频器的三种设计方法，并给出了图形设计、VHDL设计、编译结果和仿真结果。设计中采用EPM7064AETC44-7 CPLD，在QUARTUSⅡ4.2软件平台上进行。 -This paper introduces a 50% duty cycle three dividers of the three design methods, and gives the graphic design, VHDL design, compile results and the simulation results. Design used EPM7064AETC44-7 CPLD. In QUARTUS II 4.2 software platform.
Platform: | Size: 187392 | Author: li | Hits:

[Embeded-SCM Develop] fpga_digit_serial_arithmetic_1

Description: fpga/CPLD开发管理Digit-Serial DSP Functions-fpga/CPLD Development and Management of Digit-Serial DSP Functions
Platform: | Size: 2659328 | Author: liuandy | Hits:

[Embeded-SCM Develop] quartusII

Description: quartusII 中文使用手册，给广大cpld 及 fpga 开发用户使用，谢谢大家的支持。-Chinese quartusII user manual to the general development of CPLD and FPGA users, I would like to thank everyone
Platform: | Size: 2369536 | Author: hrbu | Hits:

[VHDL-FPGA-Verilog] 8080

Description: EPM1270和单片机的8080通讯接口，适合单片机与CPLD之间的高速通讯，verilog语言，QuartusII环境-EPM1270 and 8080 MCU communication interface for MCU and CPLD high-speed communication between, verilog language, QuartusII environment
Platform: | Size: 483328 | Author: 汉武帝 | Hits:

[Embeded-SCM Develop] cpld_quartus50_over

Description: 通过VERILOG HDL语言使用CPLD连接PS2键盘.-VERILOG HDL languages through the use of CPLD to connect PS2 keyboard.
Platform: | Size: 2039808 | Author: 王首浩 | Hits:

[Com Port] uart

Description: 采用CPLD实现串口通信（Verilog硬件描述语言）-Realize the use of CPLD serial communication (Verilog Hardware Description Language)
Platform: | Size: 5120 | Author: wuzhidong | Hits:

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[Communication] FPGA-UART

[Com Port] uart

[Windows Kernel] CPLD的串口程序（VHDL）

[VHDL-FPGA-Verilog] sopc

[VHDL-FPGA-Verilog] Altera_uart_VHDL

[VHDL-FPGA-Verilog] Altera_uart_Verilog

[Software Engineering] verilog50%

[Embeded-SCM Develop] fpga_digit_serial_arithmetic_1

[Embeded-SCM Develop] quartusII

[VHDL-FPGA-Verilog] 8080

[Embeded-SCM Develop] cpld_quartus50_over

[Com Port] uart

[Software Engineering] fpgadesign

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart

[Embeded-SCM Develop] UART.ZIP

[Embeded-SCM Develop] CPLD_UART

[VHDL-FPGA-Verilog] UART-CPLD

[VHDL-FPGA-Verilog] uart-code-(Verilog)

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