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[Embeded-SCM Develop] 硬件cpu&rom课程设计

Description: 这是有关cpu和存储器挂接的一个硬件课程设计，图片是用protel 99 se 画的，程序用唐都仪器调试通过，仅为一个理论性的东西。自己写的，请多指教。--It is a class written by me, which describes cpu and rom hardware design. The picture is drawn by protel 99 se. The program is passed on Tang Du instrument.
Platform: | Size: 1722368 | Author: 丁宇 | Hits:

[Other] CPU_design

Description: 一个简单指令的cpu设计。 可以实现4个指令的的运算。-a simple instructions cpu design. 4 can be achieved directive arithmetic.
Platform: | Size: 181248 | Author: 刘永 | Hits:

[Linux-Unix] complexcpu_design

Description: 主要介绍一个很好的设计思想，介绍复杂cpu设计的框图。-introduces a very good design, introduced cpu design of complex diagram.
Platform: | Size: 96256 | Author: 刘永 | Hits:

[Books] MCUDesign

Description: 《Digital Logic And Microprocessor Design With VHDL》，CPU设计经典参考书-"Digital Logic And Microprocessor Design With VHDL, "CPU design classic reference books
Platform: | Size: 4815872 | Author: hanberg | Hits:

[VHDL-FPGA-Verilog] cpuTerminate

Description: 用VHDL 编写的一个16位的cpu 设计方案，可以执行8条指令。-use VHDL to prepare a 16 cpu design of the program, the implementation of eight instructions.
Platform: | Size: 2108416 | Author: 宋文强 | Hits:

[VHDL-FPGA-Verilog] the-design-of-16-bit-cpu

Description: 用vhdl硬件语言设计的16位cpu，上传的压缩包既包含源代码又包含详细的文档说明。-with vhdl hardware design language of the 16 cpu, Upload compressed contains both the source code also contains a detailed document shows.
Platform: | Size: 128000 | Author: 晶晶 | Hits:

[Software Engineering] cpupipeline

Description: CPU设计，加法器，乘法器，除法器等，有原理讲解等。挺不错的资料-CPU design, adders, multiplier, divider and so on and so have the principle. Very good information
Platform: | Size: 1864704 | Author: 李佳 | Hits:

[Software Engineering] CPU

Description: 设计一个ＣＰＵ的具体过程，包括实验目的，逻辑图-CPU design a specific process, including experimental purposes, the logic diagram
Platform: | Size: 14336 | Author: ncf | Hits:

[Other] cpu

Description: 初学cpu设计（完全教程）包括verilog代码以及文档说明那个-Beginner cpu design (complete tutorial) includes a Verilog code as well as the document explains that
Platform: | Size: 366592 | Author: hjx | Hits:

[VHDL-FPGA-Verilog] controlunit

Description: CPU设计中的controlunit源码，其中附带了时序仿真。通过Sequencing Logic 产生 control_signals,具体的信号可在controlsignal.mif文件中直接修改。 -CPU design controlunit source, which comes with timing simulation. Sequencing Logic generated through control_signals, specific signals can directly modify the controlsignal.mif document.
Platform: | Size: 328704 | Author: ck | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 简单的16位CPU的VHDL设计 vhdl代码和cpu设计过程-Simple 16-bit CPU design of the VHDL code and VHDL design process cpu
Platform: | Size: 1488896 | Author: kilva | Hits:

[VHDL-FPGA-Verilog] MyCPU16

Description: 16位cpu设计VHDL源码，其中包括alu，clock，memory等部分的设计-16 cpu design VHDL source code, including alu, clock, memory and other parts of the design
Platform: | Size: 1089536 | Author: 孙冰 | Hits:

[VHDL-FPGA-Verilog] 8-cpu

Description: 8位CPU的VHDL设计,16条指令系统,以及部分测试代码,开发工具是quartusii_60_pc-8-bit CPU of the VHDL design, 16 instruction, as well as some of the test code, development tools is quartusii_60_pc
Platform: | Size: 3072 | Author: FJ | Hits:

[VHDL-FPGA-Verilog] RiscCPU8

Description: 可综合的VerilogHDL设计实例: ---简化的RISC 8位CPU设计简介--- -VerilogHDL be integrated design example:--- simplified RISC 8 bit CPU design Introduction---
Platform: | Size: 219136 | Author: hulin | Hits:

[ARM-PowerPC-ColdFire-MIPS] CPU

Description: CPU 设计，不错的哦，顶一下哈，希望大家都弄成免费的-CPU design, good Oh, the top click Kazakhstan, I hope we all have to face free
Platform: | Size: 2110464 | Author: kukuyeyewa | Hits:

[VHDL-FPGA-Verilog] The_design_of_MIPS_CPU(VHDL)

Description: MIPS CPU设计实例的完整文档，台湾一个大学生的MIPS CPU完整设计文档，内附设计代码。-a complete document of MIPS CPU design , a Taiwan university students complete MIPS CPU design document, containing the design code.
Platform: | Size: 918528 | Author: 李皓 | Hits:

[Other] cpu

Description: 基于MIPS指令集的32位CPU设计与VHDL实现-Based on the MIPS instruction set of the 32-bit CPU design and the realization of VHDL
Platform: | Size: 10553344 | Author: gy | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 八位简单risc cpu 设计的源代码，VHDL语言写的-8 Simple risc cpu design source code, VHDL language written
Platform: | Size: 215040 | Author: yishi | Hits:

[Embeded-SCM Develop] CPU

Description: 利用VHDL语言 开发设计一个小型CPU -Development and design using VHDL, a small CPU
Platform: | Size: 201728 | Author: 隐士 | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 一个完整的流水CPU设计，quartus平台，Verilog实现-CPU design a complete water, quartus platform, Verilog realization
Platform: | Size: 1100800 | Author: 涯 | Hits:
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