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Description: 用Verilog编写crc校验码，包括8位，12位，16位，32位，非常实用
Platform: |
Size: 11138 |
Author: asd |
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Description: 这是一个在FPGA上实现CRC算法的程序，包含了CRC-8,CRC-12,CRC-16,CRC-CCIT,CRC-32一共五种校验形式。
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Size: 10591 |
Author: 李奥运 |
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Description: CRC12代码,查表法和计算法比较,可以得出明确的时间效应.-CRC12 code look-up table method and computation of comparison, it is clearly time effect.
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Size: 6144 |
Author: zzc |
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Description: CRC循环冗余编码程序实现，程序简单功能齐备-Cyclic Redundancy Code program, a simple functional completeness
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Size: 6144 |
Author: lulu |
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Description: 用Verilog编写crc校验码，包括8位，12位，16位，32位，非常实用-Prepared using Verilog CRC check codes, including 8, 12, 16, 32, a very practical
Platform: |
Size: 11264 |
Author: asd |
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Description: (1) 315、433、868、915Mh的ISM 和SRD频段
(2) 最高工作速率500kbps，支持2-FSK、GFSK和MSK调制方式
(3) 高灵敏度（1.2kbps下-110dDm，1％数据包误码率）
(4) 内置硬件CRC 检错和点对多点通信地址控制
(5) 较低的电流消耗（RX中，15.6mA，2.4kbps,433MHz）
(6) 可编程控制的输出功率，对所有的支持频率可达+10dBm
(7) 支持低功率电磁波激活功能
(8) 支持传输前自动清理信道访问（CCA），即载波侦听系统
(9) 快速频率变动合成器带来的合适的频率跳跃系统
(10) 模块可软件设地址，软件编程非常方便
(11) 标准DIP间距接口，便于嵌入式应用
(12) 单独的64字节RX和TX数据FIFO-(1) 315,433,868,915 Mh of the ISM and SRD frequency bands (2) maximum rate of 500kbps, support for 2-FSK, GFSK and MSK modulation (3) high sensitivity (1.2kbps under-110dDm, 1 packet error bit-rate) (4) built-in hardware CRC error detection and control of point-to-multipoint communication address (5) a lower current consumption (RX in, 15.6mA, 2.4kbps, 433MHz) (6) programmable control of output power for all the support frequencies up to+ 10dBm (7) to support low-power electromagnetic wave activation (8) to support the transmission before the automatic clean-up Channel Access (CCA), namely Carrier Sense System (9) Fast frequency synthesizer brought about by changes in suitable frequency hopping system (10) modules can be software-based address, software programming is easy (11) standard DIP spacing interfaces for embedded applications (12) separate 64-byte RX and TX data FIFO
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Size: 319488 |
Author: 李华力 |
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Description: 这是一个在FPGA上实现CRC算法的程序，包含了CRC-8,CRC-12,CRC-16,CRC-CCIT,CRC-32一共五种校验形式。-err
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Size: 10240 |
Author: 李奥运 |
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Description:
循环冗余码校验英文名称为Cyclical Redundancy Check，简称CRC。它是利用除法及余数的原理来作错误侦测（Error Detecting）的。实际应用时，发送装置计算出CRC值并随数据一同发送给接收装置，接收装置对收到的数据重新计算CRC并与收到的CRC相比较，若两个CRC值不同，则说明数据通讯出现错误。
根据应用环境与习惯的不同，CRC又可分为以下几种标准：
①CRC-12码；
②CRC-16码；
③CRC-CCITT码；
④CRC-32码。
CRC-12码通常用来传送6-bit字符串。CRC-16及CRC-CCITT码则用是来传送8-bit字符，其中CRC-16为美国采用，而CRC-CCITT为欧洲国家所采用。CRC-32码大都被采用在一种称为Point-to-Point的同步传输中。
下面以最常用的CRC-16为例来说明其生成过程。-err
Platform: |
Size: 3072 |
Author: qizhiwei |
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Description: CCITT的CRC16代码，自己编写的已通过验证，注意和Matlab的CRC函数有所不同。-This script calculates the 16-bit ITU-T CRC. The generator polynomial is G(x)=1+ X^5+ X^12+ X^16
Platform: |
Size: 1024 |
Author: 张原 |
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Description: crc的原理以及格式，和并行crc的代码．另外一个是rfid的协议标准-crc datasheet and parallel code design.
another pdf is rfid 14443 spec chinese version.
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Size: 331776 |
Author: 老六 |
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Description: CRC效验程序，使用CRC-16和CRC-CCITT方法。
其中CRC-16的效验字是: X^16 + X^15 + X^2 + 1,CRC-12的效验字是: X^12 + X^11 + X^3 + X^2 + X^1 +1 CRC-CCITT的效验字是: X^16 + X^12 + X^5 + 1
-CRC-tested program, using the CRC-16 and CRC-CCITT method. Including CRC-16' s efficacy word is: X ^ 16+ X ^ 15+ X ^ 2+ 1 CRC-12' s efficacy word is: X ^ 12+ X ^ 11+ X ^ 3+ X ^ 2+ X ^ 1+ 1 CRC-CCITT efficacy of the word is: X ^ 16+ X ^ 12+ X ^ 5+ 1
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Size: 1024 |
Author: spencer |
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Description: 自动完成CRC校验码的计算
1 010110001101
110011
可以得到:
(1)index:5 pointing:1
101011
110011
011000
(2)index:6 pointing:0
110000
110011
000011
(3)index:7 pointing:0
000110
0
000110
(4)index:8 pointing:0
001100
0
001100
(5)index:9 pointing:1
011001
0
011001
(6)index:10 pointing:1
110011
110011
000000
(7)index:11 pointing:0
000000
0
000000
(8)index:12 pointing:1
000001
0
000001
-CRC check code automatically derive the 1-1,010,110,001,101,110,011 can be: (1) index: 5 pointing: 1 101011 110011 011000 (2) index: 6 pointing: 0 110000 110011 000011 (3) index: 7 pointing: 0 000110 0 000110 (4) index: 8 pointing: 0 001100 0 001100 (5) index: 9 pointing: 1 011001 0 011001 (6) index: 10 pointing: 1 110011 110011 000000 (7) index: 11 pointing: 0 000000 0 000000 (8 ) index: 12 pointing: 1 000001 0 000001
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Size: 1024 |
Author: 夏治文 |
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Description: IAR Asm for MSP430.
Calculate the CCITT/ITU/CRC-16
parameters for this CRC are:
Polynomial: x^16 + x^12 + x^5 + 1 (0x1021)
Start value 0xFFFF
Data receives from USART
Checksum in R11.-IAR Asm for MSP430.
Calculate the CCITT/ITU/CRC-16
parameters for this CRC are:
Polynomial: x^16 + x^12 + x^5 + 1 (0x1021)
Start value 0xFFFF
Data receives from USART
Checksum in R11.
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Size: 2048 |
Author: vlad |
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Description: 一個CRC-12計算的串入式電路並下載至FPGA電路板-FPGA CRC-16
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Size: 1024 |
Author: TAE |
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Description: Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data
communication systems and other serial data transmission systems. CRC is based on
polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy
Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note
discusses the implementation of an IEEE 802.3 CRC in a Virtex™ device. The reference
design provided with this application note provides Verilog point solutions for CRC-8, CRC-12,
CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also
included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32), any
polynomial, and any data input width.-Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex ™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8 , CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32 ), any polynomial, and any data input width.
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Size: 90112 |
Author: 尤恺元 |
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Description: CRC校验代码，包含6bit\8bit\12bit\16bit\32bit
查表法和移位法-CRC checksum code, including 6bit \ 8bit \ 12bit \ 16bit \ 32bit lookup table and shift method
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Size: 17408 |
Author: luice |
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Description: CRC-6 CRC-8 CRC-12 CRC-16 CRC-32等查表和移位实现，相关部分可以参考。-CRC-6 CRC-8 CRC-12 CRC-16 CRC-32 and other look-up and shift to achieve, you can refer to the relevant section.
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Size: 17408 |
Author: maikeyiwen |
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Description: CRC校验参考设计Verilog代码,crc8,16,32bit- crc8_8.v : CRC-8, 8-bit data input.
crc12_4.v : CRC-12, 4-bit data input.
crc16_8.v : CRC-16, 8-bit data input.
crc_ccit_8.v : CRC-CCIT, 8-bit data input.
crc32_8.v : CRC-32, 8-bit data input.
Platform: |
Size: 10240 |
Author: guangngqiang |
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Description: 包括下面文档：
readme.txt : This file
crc8_8.v : CRC-8, 8-bit data input.
crc12_4.v : CRC-12, 4-bit data input.
crc16_8.v : CRC-16, 8-bit data input.
crc_ccit_8.v : CRC-CCIT, 8-bit data input.
crc32_8.v : CRC-32, 8-bit data input.
crcgen.pl : Perl script used to generate Verilog Source for CRC
caluculation.(Contains the following files
readme.txt : This file
crc8_8.v : CRC-8, 8-bit data input.
crc12_4.v : CRC-12, 4-bit data input.
crc16_8.v : CRC-16, 8-bit data input.
crc_ccit_8.v : CRC-CCIT, 8-bit data input.
crc32_8.v : CRC-32, 8-bit data input.
crcgen.pl : Perl script used to generate Verilog Source for CRC
caluculation.)
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Size: 10240 |
Author: chris_lj
|
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Description: CRC32:polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) * data width: 8
CRC16:polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) * data width: 8
Platform: |
Size: 2048 |
Author: FYSG |
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