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[ARM-PowerPC-ColdFire-MIPS] crc16_8bit.v

Description: 利用verilog硬件描述语言编写的8为并行输入的常crc校验模块。hdlc子模块-Using Verilog hardware description language for the parallel importation of 8 regular CRC checksum module. HDLC sub-modules
Platform: | Size: 1024 | Author: 张纪强 | Hits:

[VHDL-FPGA-Verilog] crccode

Description: CRC循环冗余检验 Verilog 编码程序-CRC cyclic redundancy test Verilog coding procedures
Platform: | Size: 1024 | Author: yuanxiaonan | Hits:

[VHDL-FPGA-Verilog] CRC

Description: verilog 实现循环冗余校验 源代码-Cyclic Redundancy Check realize Verilog source code
Platform: | Size: 367616 | Author: 长空 | Hits:

[VHDL-FPGA-Verilog] crc_d8

Description: Verilog module containing a synthesizable CRC function // * polynomial: (0 1 8) // * data width: 8-Verilog module containing a synthesizable CRC function //* polynomial: (0 1 8) //* data width: 8
Platform: | Size: 1024 | Author: yangyi | Hits:

[VHDL-FPGA-Verilog] crc_verilog_xilinx

Description: 这是一个在FPGA上实现CRC算法的程序，包含了CRC-8,CRC-12,CRC-16,CRC-CCIT,CRC-32一共五种校验形式。-err
Platform: | Size: 10240 | Author: 李奥运 | Hits:

[Communication] crc_check

Description: CRC校验，包括crc8_4、crc12_4、crc16_8、crc32_8-CRC checksum, including crc8_4, crc12_4, crc16_8, crc32_8
Platform: | Size: 4096 | Author: wl | Hits:

[Crack Hack] crc16

Description: 16bit CRC for 8bits data
Platform: | Size: 1024 | Author: 苗淼 | Hits:

[Software Engineering] CRC

Description: 　本文提出一种通用的CRC 并行计算原理及实现方法,适于不同的CRC 生成多项式和不同并行度(如8 位、16 位、及32 位等) ,与目前已采用的查表法比较,不需要存放余数表的高速存储器,减少了时延,且可通过增加并 行度来降低高速数传系统的CRC 运算时钟频率.-In this paper, a universal principle of CRC and implementation of parallel computing methods for generating different CRC polynomial and different degree of parallelism (eg, 8, 16, and 32-bit, etc.), with the current look-up table method has been used in comparison do not store more than a few tables, high-speed memory, reducing latency, and degree of parallelism can be increased to reduce the high-speed data-transmission system clock frequency of the CRC computation.
Platform: | Size: 144384 | Author: 黑月 | Hits:

[Embeded-SCM Develop] CRC

Description: CRC和线性码程序 可能对初级学习有用 希望能够好好利用-CRC
Platform: | Size: 30720 | Author: 黄金刚 | Hits:

[Other] crc

Description: 循环冗余校验码CRC的VerilogHDL源程序-CRC cyclic redundancy check code of the source VerilogHDL
Platform: | Size: 1024 | Author: hh | Hits:

[Software Engineering] CRC8

Description: it is a crc on 8 bytes
Platform: | Size: 762880 | Author: om | Hits:

[VHDL-FPGA-Verilog] crc_verilog_xilinx

Description: CRC,对于研究通信的有重要意义.利用VERILOG实现8位，16位等CRC原理,-CRC, the study of communication are important. VERILOG to achieve the use of 8, 16, such as CRC principle,
Platform: | Size: 10240 | Author: | Hits:

[VHDL-FPGA-Verilog] trunk-hdlc

Description: 高级链路层协议的实现，vhdl，fpga-- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern is assumed only after the end of a frame which is signaled by an abort signal - Zero insertion - Abort pattern generation and checking - Address insertion and detection by software - CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used) - FIFO buffers and synchronization (External) - Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted) - Q.921, LAPB and LAPD compliant. - For complete specifications refer to spec document
Platform: | Size: 188416 | Author: | Hits:

[source in ebook] crc8

Description: 8bit CRC码生成器vhdl 代码，延时一个周期CRC码有效。-8bit crc code genergator,after delay one clock,crc code valid
Platform: | Size: 1024 | Author: luoda | Hits:

[VHDL-FPGA-Verilog] module-Temperature

Description: DS18B20引脚功能 GND地，DQ数据总线，VDD电源电压 18B20共有三种形式的存储器资源，它们分别是： ROM 只读存储器，用于存放DS18B20ID编码，其前八位是单线系列编码，后面48位是芯片唯一的序列号，最后8位是以上56位的CRC码。DS18B20共64位ROM RAM 数据暂存器，数据掉电后丢失，共9个字节，每个字节8位，第1、2个字节是温度转换后的数据值信息，EEPROM 非易失性记忆体，用于存放长期需要保存的数据，上下限温度报警值和校验数据 -DS18B20 Function GND Ground pin, DQ data bus, VDD supply voltage 18B20 There are three forms of memory resources, they are: ROM read-only memory for storing DS18B20ID coding, the top eight single-family is encoded, followed by 48 is the chip serial number only, over the last eight is 56-bit CRC code. DS18B20 total of 64-bit ROM RAM data store, data loss after power-down, a total of 9 bytes, each byte 8-bit, 1, 2 bytes of temperature data converted value information, EEPROM non-volatile volatile memory for storage of long-term need to preserve data, upper and lower temperature alarm and calibration data
Platform: | Size: 9216 | Author: 袁亚楠 | Hits:

[VHDL-FPGA-Verilog] CRC-8

Description: VHDL code for CRC-8 computing using 32 bit input (parallel)
Platform: | Size: 1024 | Author: stefanovic | Hits:

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