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[Embeded-SCM Develop卷积码、CRC

Description: 卷积码的C源程序,包括编码器和译码器。 还有一个是循环荣誉校验的vhdl]源码。-convolution of C source code, including the encoder and decoder. There is a cycle of the calibration honor VHDL] source.
Platform: | Size: 6873 | Author: 潘华林 | Hits:

[Embeded-SCM Develop卷积码、CRC

Description: 卷积码的C源程序,包括编码器和译码器。 还有一个是循环荣誉校验的vhdl]源码。-convolution of C source code, including the encoder and decoder. There is a cycle of the calibration honor VHDL] source.
Platform: | Size: 6144 | Author: 潘华林 | Hits:

[VHDL-FPGA-Verilogcrc_verilog

Description: 循环码编码器verilog实现,里面包含有源程序和仿真图。-Cyclic code encoder Verilog realization, which contains the source code and simulation of Fig.
Platform: | Size: 15360 | Author: 萍果 | Hits:

[VHDL-FPGA-Verilogcrcm

Description: crc 校验,vhdl源码,经仿真能正常运行,供大家参考-CRC checksum, vhdl source, the simulation can be normal operation, for your reference
Platform: | Size: 1024 | Author: fangliang | Hits:

[VHDL-FPGA-VerilogCRC16bits

Description: 16bit crc encoder ande demo
Platform: | Size: 167936 | Author: chen | Hits:

[Crack Hack80300di

Description: this a vhdl program for crc encoder and decoder-this is a vhdl program for crc encoder and decoder
Platform: | Size: 194560 | Author: mohit | Hits:

[Othervenomgen

Description: venomgen - C source code of VHDL code generator for CRC, BCH and RS encoder -venomgen- C source code of VHDL code generator for CRC, BCH and RS encoder * polynomials can be entered via command line * variable bus width * automatic testbench generation
Platform: | Size: 258048 | Author: Michael Lau | Hits:

[VHDL-FPGA-Verilogcrc

Description: 基于VHDL的CRC编码器的CRC的生成模块源码。-The CRC based on VHDL CRC encoder source code generation module.
Platform: | Size: 10240 | Author: 段志伟 | Hits:

[VHDL-FPGA-Verilogcrc

Description: 基于VHDL的CRC编码器的检错模块的源码-The VHDL-based CRC error detection encoder module source
Platform: | Size: 10240 | Author: 段志伟 | Hits:

[Embeded-SCM Develop卷积码、CRC

Description: 卷积码的C源程序,包括编码器和译码器。还有一个是循环荣誉校验的vhdl]源码。-convolution of C source code, including the encoder and decoder. There is a cycle of the calibration honor VHDL] source.
Platform: | Size: 7168 | Author: signific | Hits:

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