Search - Carry lookahead

[WEB Code] ripple-lookahead-carryselect-adder

Description: Ripple Adder: 16-bit 全加,半加及ripple adder的设计及VHDL程序 Carry Look ahead Adder:4, 16, 32 bits 前置进位加法器的设计方案及VHDL程序 Carry Select Adder:16 Bits 进位选择加法器的设计方案及VHDL程序-Ripple Adder : 16-bit full adder, semi-Canada and the ripple adder design and VHDL procedures Carry Look ahead Adder : 4, 16, 32 bits front rounding Adder and the VHDL design procedures Carry Select Adder : 16 Bits Progressive Choice Adder design and VHDL - sequence
Platform: | Size: 15972 | Author: 李成 | Hits:

[Linux-Unix] cla_dc

Description: a demo script of \"carry lookahead adder\" for synopsys design compiler
Platform: | Size: 1906 | Author: heyong | Hits:

[Linux-Unix] cla_src

Description: carry lookahead adder verilog program
Platform: | Size: 1575 | Author: heyong | Hits:

[Documents] ripple-lookahead-carryselect-adder

Description: Ripple Adder: 16-bit 全加,半加及ripple adder的设计及VHDL程序 Carry Look ahead Adder:4, 16, 32 bits 前置进位加法器的设计方案及VHDL程序 Carry Select Adder:16 Bits 进位选择加法器的设计方案及VHDL程序-Ripple Adder : 16-bit full adder, semi-Canada and the ripple adder design and VHDL procedures Carry Look ahead Adder : 4, 16, 32 bits front rounding Adder and the VHDL design procedures Carry Select Adder : 16 Bits Progressive Choice Adder design and VHDL- sequence
Platform: | Size: 15360 | Author: 李成 | Hits:

[Linux-Unix] cla_dc

Description: a demo script of "carry lookahead adder" for synopsys design compiler
Platform: | Size: 2048 | Author: heyong | Hits:

[Linux-Unix] cla_src

Description: carry lookahead adder verilog program
Platform: | Size: 1024 | Author: heyong | Hits:

[Windows Develop] lookahead

Description: implement of carry look ahead adder vith verilog
Platform: | Size: 32768 | Author: shabnam | Hits:

[Algorithm] CLAA_32_BITS

Description: A 32-bit carry lookahead adder
Platform: | Size: 1024 | Author: yasser01 | Hits:

[VHDL-FPGA-Verilog] VHDL-ripple-lookahead-carryselect-adder

Description: vhdl code for ripple carry adder, carry select adder and carry look ahead adder
Platform: | Size: 17408 | Author: praveen | Hits:

[VHDL-FPGA-Verilog] carry-lookahead-adder

Description: ddr 2 model by jaswant singh
Platform: | Size: 849920 | Author: jaswant singh | Hits:

[VHDL-FPGA-Verilog] adder

Description: 设计一个16×16位的流水线乘法器。乘法器部分采用16×16进位保留（Carry-save）阵列构成。最后一行部分积产生单元要求采用超前进位构成。 -Design of a 16 x 16 pipelined multiplier. Multiplier by 16 x 16 carry save array ( Carry-save ). The last line of the partial product generation unit requires use of carry lookahead.
Platform: | Size: 2048 | Author: raul | Hits:

[VHDL-FPGA-Verilog] lab1

Description: 一个21位先行进位加法器的代码交作业和毕设必备，自己写的，不完全地方请指出 -A 21-bit carry-lookahead adder code homework and must complete set up, wrote it myself, not exactly place please indicate
Platform: | Size: 3072 | Author: lu | Hits:

[VHDL-FPGA-Verilog] add4_fast_carry

Description: 一个4位超前几位加法器的设计，在modelsim中仿真通过。-This is a carry lookahead adder design, which is simulated successfully in modelsim.
Platform: | Size: 70656 | Author: zhouwen | Hits:

[VHDL-FPGA-Verilog] EX8

Description: 累计进位加法器和超前进位加法器，数字逻辑课程作业-Cumulative carry lookahead adder and adder, digital logic course work
Platform: | Size: 200704 | Author: silverymoon | Hits:

[Other] CLA

Description: CLA adder:use vhdl to write the carry-lookahead adder which is a type of adder used in digital logic-CLA adder
Platform: | Size: 1024 | Author: awen | Hits:

[VHDL-FPGA-Verilog] con_addr_32

Description: 因为二进制加法的进位只可能是1或0，所以可以将32位加法器分为8块（最低一块由4位先行进位加法器直接构成，其余加法结构都采用先行进位加法器结构）分别进行加法计算，除最低位以外的其他7块加法器结构各复制两份，进位输入分别预定为1和0。于是，8块加法器可以同时进行各自的加法运算，然后根据各自相邻低位加法运算结果产生的进位输出，选择正确的加法结果输出。-Because binary adder carry only be 1 or 0, so it can be 32-bit adder is divided into eight (minimum one by the four carry-lookahead adder directly constitute the remaining adder structures using carry-lookahead adder structure), respectively Addition calculation, in addition to other than the lowest seven two copies of each adder structure, carry input is scheduled for 1 and 0, respectively. Thus, the adder 8 can be performed simultaneously the respective adder, and then the respective adjacent low addition result generated carry bit output, select the correct output of the addition result.
Platform: | Size: 2048 | Author: Peter | Hits:

[Other] claa

Description: vhdl code for carry lookahead addder
Platform: | Size: 1024 | Author: sreenath | Hits:

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[WEB Code] ripple-lookahead-carryselect-adder

[Linux-Unix] cla_dc

[Linux-Unix] cla_src

[Documents] ripple-lookahead-carryselect-adder

[Linux-Unix] cla_dc

[Linux-Unix] cla_src

[Windows Develop] lookahead

[Algorithm] CLAA_32_BITS

[VHDL-FPGA-Verilog] VHDL-ripple-lookahead-carryselect-adder

[VHDL-FPGA-Verilog] carry-lookahead-adder

[VHDL-FPGA-Verilog] adder

[VHDL-FPGA-Verilog] lab1

[VHDL-FPGA-Verilog] add4_fast_carry

[VHDL-FPGA-Verilog] EX8

[Other] CLA

[VHDL-FPGA-Verilog] con_addr_32

[Other] claa

[VHDL-FPGA-Verilog] 32bit_add

[Other] carry-look-ahead

[VHDL-FPGA-Verilog] 32-bit Carry lookahead adder

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