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Description: 本代码介绍了使用VHDL开发FPGA的一般流程，最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL，在软件开发平台ISE上完成，可以在较高速时钟频率（100MHz）下正常工作。该设计的频率计能准确的测量频率在1Hz到100MHz之间的信号。使用ModelSim仿真软件对VHDL程序做了仿真，并完成了综合布局布线，最终下载到芯片Spartan-II上取得良好测试效果。-the code on the FPGA using VHDL development of the general process, finally adopted a FPGA-based digital frequency method. The design using VHDL hardware description language, the software development platform ISE completed, the higher speed clock frequency (100MHz) under normal work. The design of the frequency meter can be accurately measured in a frequency of 100MHz between Hz signal. Use ModelSim VHDL simulation software to do the simulation process, and completed a comprehensive layout cabling, downloaded to the final chip Spartan-II made good on the test results.
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Size: 514889 |
Author: 许的开 |
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Description: 本代码介绍了使用VHDL开发FPGA的一般流程，最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL，在软件开发平台ISE上完成，可以在较高速时钟频率（100MHz）下正常工作。该设计的频率计能准确的测量频率在1Hz到100MHz之间的信号。使用ModelSim仿真软件对VHDL程序做了仿真，并完成了综合布局布线，最终下载到芯片Spartan-II上取得良好测试效果。-the code on the FPGA using VHDL development of the general process, finally adopted a FPGA-based digital frequency method. The design using VHDL hardware description language, the software development platform ISE completed, the higher speed clock frequency (100MHz) under normal work. The design of the frequency meter can be accurately measured in a frequency of 100MHz between Hz signal. Use ModelSim VHDL simulation software to do the simulation process, and completed a comprehensive layout cabling, downloaded to the final chip Spartan-II made good on the test results.
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Size: 515072 |
Author: 许的开 |
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Description: 这是一个可以设置系统时间的程序，按一定的规则进行系统时间的锁定。这个程序说明原理。还有一个正式版。主要差异是系统时钟在WINDOWS下准确与否。-This is a can set the system time-consuming procedures, according to certain rules of the lock system time. The description of the procedures for Principle. There is also a final version. The main difference between the system clock is accurate or not, under the WINDOWS.
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Size: 6144 |
Author: gt0005 |
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Description: 【设计题目】
多功能数字钟的设计
【设计目的】
1掌握数字系统的分析和设计方法
2能够熟练的、合理的选用集成电路器件
3熟悉EWB软件的使用。
【设计指标及要求】
设计一个多功能数字钟，以一昼夜24小时为一个计数周期。准确计时，具有“时”“分”“秒”数字显示。整点能自动打点、报时。要求报时声响四低一高，最后一响为整点。具有校时功能。要求电路主要采用中小规模CMOS集成电路。要求电路尽量简化，并选用同类型的器件。在EWB电子工作平台上进行电路的设计和计算机仿真。
-Title] [design multi-functional digital clock design 1] [designed to exploit the digital system analysis and design method of 2 to skilled, reasonable choice of integrated circuit device 3 familiar with the EWB software. [] Design specifications and requirements to design a multi-function digital clock, 24 hours a day for a cycle count. Accurate time, a when sub seconds The figures show. Automatically runs the whole point, the newspaper. Four-time low noise requirements of a high, the final point for the whole ring. With a school function. Requirements are mainly small and medium-sized circuits CMOS integrated circuits. Asked the circuit as simple as possible and select the same type of device. EWB work in the platform of electronic circuit design and computer simulation.
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Size: 197632 |
Author: petyfer |
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Description: 设计一个21点游戏，要求可以人人对战，要有游戏界面，可以由电脑判断输赢情况。
计算模型：由于要涉及到洗牌和发牌所以要由随机函数进行洗牌，通过for语句进行发牌，最后通过将每个人的点数相加得到总点数，进而判断输赢。
设计方案：用VC环境来设计游戏的界面，包括发牌按钮，拒绝要牌按钮，判断胜负按钮，以及牌和最终胜负的输出显示框。使用C语言并配合MFC进行程序的设计。-The design of a 21 o clock game, everyone is asking for war, we need to have the game interface, you can determine the winning or losing the case by computer. Calculation model: As the need to relate to shuffle and licensing it is necessary to carry out random shuffle function, through the for statement to conduct the licensing, and finally through the points of each person to be the total sum of points, and then judge the winning or losing. Design options: with VC games environment to design the interface, including the licensing button, and refused to license button, to determine the outcome of the button, as well as licensing and final outcome of the output display box. The use of C language and carry out procedures with MFC design.
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Size: 624640 |
Author: miao |
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Description: 使用VHDL语言编程，烧录在芯片运行的倒数5秒响4声短铃最后一声长音的数字钟-The use of VHDL language programming, burn in the chip to run the last 5 seconds short bell ring 4 final say sound a long tone of digital clock
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Size: 1024 |
Author: zhyanh1118 |
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Description: 这是我自己编写的一个键盘输入的闹钟定时程序，由于本人的开发板上只有4位数码管，所以只能显示分和秒（分可以写到99，秒只能写最大60）。运行成功。可能代码不够简洁，但条理清晰。-This is what I have written a regular keyboard input of the alarm clock procedures, developed as a result of my board, only four digital tube, we can only show the minutes, and seconds (99 minutes to write, writing can only be the greatest 60 seconds). Successful operation. Code may be simple enough, but the clarity.
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Size: 21504 |
Author: yongchang |
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Description: 微机课程设计 电子时钟 功能： 计时，响铃，调时，串口修改时间-Computer curriculum design features electronic clock: time, ringing, when transferred, serial modified
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Size: 2048 |
Author: soledad |
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Description: 大学毕业设计作品：出租车计价器的设计：以AT89S52单片机为中心，通过金属传感器来测距，实现对出租车的计价统计。结合语音芯片ISD4004，时钟芯片DS1302，功放模块LM386N组成语音时间控制系统，最后通过液晶显示模块LCD12864显示单价、路程、总价、时间等。本系统可以实现单价、起步价、白天价、夜间价的显示和时间的修改。AT89S52通过P0口与外部语音报价电路相连，可以实现语音报价功能。-Graduated from college design work: the design of a taxi meter: The AT89S52 microcontroller as the center, ranging through the metal sensor to achieve statistical valuation of the taxi. Combination of voice chip ISD4004, clock chip DS1302, composed of voice amplifier module LM386N-time control system, the final adoption of liquid crystal display module LCD12864 show unit price, distance, total price and time. This system can achieve unit price, starting at daytime price, prices shown at night and the time changes. AT89S52 through the P0 port with an external circuit connected to voice offer, you can offer voice functionality.
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Size: 7168 |
Author: qinyu |
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Description: 一个用VHDL语言编写的十进制计数器，后续还有分频器、数据选择器、七段数码显示程序等软件平台是Quartus II 7.2 ，最后通过这些小的模块可以组合起来制作出一个时钟或者其它的任意进制计数器，适合初学者，通过这些程序，刚接触VHDL的学习者可以一步步的去认识和了解VHDL，最后通过设计一个具有实用功能的电路，来增加学习者的成就感和学习兴趣。所有程序软硬件调试都成功通过，硬件平台是自己学校设计的一块开发板，要了解的可以联系本人。联系QQ：782649157 -VHDL language using a decimal counter, follow-up there is divider, data selector, seven-segment digital display procedures, the software platform is Quartus II 7.2, the final adoption of these small modules can be combined to produce a clock or other arbitrary binary counter, suitable for beginners, through these procedures, new to VHDL learners can be a step by step to the awareness and understanding of VHDL, the last through the design of a practical function of the circuit, to increase the learner' s sense of achievement and interest in learning. All programs have successfully passed the hardware and software debugging, hardware platform is designed by a development of their own school board, it is necessary to know can contact me. Contact QQ: 782649157
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Size: 242688 |
Author: QQ |
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Description: 一个用VHDL语言编写的1/16分频器，后续还有计数器、数据选择器、七段数码显示程序等软件平台是Quartus II 7.2 ，最后通过这些小的模块可以组合起来制作出一个时钟或者其它的任意进制计数器，适合初学者，通过这些程序，刚接触VHDL的学习者可以一步步的去认识和了解VHDL，最后通过设计一个具有实用功能的电路，来增加学习者的成就感和学习兴趣。所有程序软硬件调试都成功通过，硬件平台是自己学校设计的一块开发板，要了解的可以联系本人。联系QQ：782649157 -Written in VHDL language using a 1/16 divider, follow-up there is the counter, data selector, seven-segment digital display procedures, the software platform is Quartus II 7.2, the final adoption of these small modules can be combined to produce a clock or other arbitrary binary counter, suitable for beginners, through these procedures, new to VHDL learners can be a step by step to the awareness and understanding of VHDL, the last through the design of a practical function of the circuit, to increase the learner s sense of achievement and motivation in learning . All programs have successfully passed the hardware and software debugging, hardware platform is designed by a development of their own school board, it is necessary to know can contact me. Contact QQ: 782649157
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Size: 226304 |
Author: QQ |
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Description: Written in VHDL language using a 1 / 16 divider, follow-up there is the counter, data selector, seven-segment digital display procedures, the software platform is Quartus II 7.2, the final adoption of these small modules can be combined to produce a clock or other arbitrary binary counter, suitable for beginners, through these procedures, new to VHDL learners can be a step by step to the awareness and understanding of VHDL, the last through the design of a practical function of the circuit, to increase the learner s sense of achievement and motivation in learning . All programs have successfully passed the hardware and software debugging, hardware platform is designed by a development of their own school board, it is necessary to know can contact me. Contact QQ: 782649157-Written in VHDL language using a 1/16 divider, follow-up there is the counter, data selector, seven-segment digital display procedures, the software platform is Quartus II 7.2, the final adoption of these small modules can be combined to produce a clock or other arbitrary binary counter, suitable for beginners, through these procedures, new to VHDL learners can be a step by step to the awareness and understanding of VHDL, the last through the design of a practical function of the circuit, to increase the learner' s sense of achievement and motivation in learning. All programs have successfully passed the hardware and software debugging, hardware platform is designed by a development of their own school board, it is necessary to know can contact me. Contact QQ: 782649157
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Size: 230400 |
Author: QQ |
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Description: 一个用VHDL语言编写的七段数码管显示程序，后续还有分频器、数据选择器、计数器程序等软件平台是Quartus II 7.2 ，最后通过这些小的模块可以组合起来制作出一个时钟或者其它的任意进制计数器，适合初学者，通过这些程序，刚接触VHDL的学习者可以一步步的去认识和了解VHDL，最后通过设计一个具有实用功能的电路，来增加学习者的成就感和学习兴趣。所有程序软硬件调试都成功通过，硬件平台是自己学校设计的一块开发板，要了解的可以联系本人。联系QQ：782649157 -Written in VHDL language using a seven-segment digital tube display program, follow-up there is divider, data selector, counters procedures, software platform is Quartus II 7.2, the final adoption of these small modules can be combined to produce a clock or other arbitrary binary counter, suitable for beginners, through these procedures, new to VHDL learners can be a step by step to the awareness and understanding of VHDL, the last through the design of a practical function of the circuit, to increase the learner' s sense of achievement and interest in learning. All programs have successfully passed the hardware and software debugging, hardware platform is designed by a development of their own school board, it is necessary to know can contact me. Contact QQ: 782649157
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Size: 234496 |
Author: QQ |
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Description: 用动态扫描方法和定时器1在数码管的前三位显示出秒表，
精确到1 秒，即最后一位显示1 秒，一直循环下去
设时钟频率为12M-Dynamic scanning method and a digital timer control of the top three shows a stopwatch, accurate to 1 of the second and final one showed 1 of the second, has been set clock cycle continues 12M
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Size: 1024 |
Author: 毛佳俊 |
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Description: a)实现时钟功能，可以在两个七段数码管上显示秒钟时间或者分钟时间，用一个开关控制两者的切换。
b)实现闹钟功能，时间到播放一段音乐，并在发光二极管上播放走马灯图案，在双色点阵发光二极管上滚动显示自己的学号。能控制滚动显示的速度以及音乐播放的速度，且用一个开关控制闹钟的开关。-a) achieve clock function, can be in two seven-segment digital tube display seconds or minutes, with a switch control to switch between the two. b) to achieve clock function, time to play some music, and play a revolving door in the light-emitting diode design, the two-color LED on the scrolling dot matrix display their student number. Can control the speed of scrolling display and music playback, and alarm clock with a switch control switch.
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Size: 2048 |
Author: lisi |
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Description: This module contains a digital clock which can enables clock setup option and up to four alarms. This was targeted Virtex-5 FPGA (ML501) and interfaced with LCD display. and center, north and east push buttons.
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Size: 1090560 |
Author: mvnvprasad |
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Description: 用汇编语言写的一个时钟程序，带有闹钟功能。同时后台运行时间，不断刷新。可设置闹钟，可设置定时器。-Written in assembly language program, a clock with alarm function. Time while running in the background, constantly refreshed. To set the alarm, can set the timer.
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Size: 553984 |
Author: lin |
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Description: 单片机 1602 显示时钟 其中有详细的步骤 从只显示秒，到秒显示正常，再到时钟显示正常，最后到按键可以控制调节-SCM 1602 shows the clock including a detailed step from only seconds to the second display is normal, then the clock display properly, you can control the final adjustment to the key
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Size: 25600 |
Author: 彭甲 |
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Description: 功能：读取DS1302时间，包括小时和分钟，并送时钟数码管显示
key1，实现循环切换小时十位、小时个位、分钟十位、分钟个位、退出设置等功能；当切换到对应位时，对应位闪烁！
key2: 修改对应的时间值， 实现加1功能，根据key1cnt的值，修改对应的位 ，如key1cnt=1，则修改小时十位，且每按1次，该位加1. ，
key3: 实现修改，将key2设置的小时分钟写入DS1302，修改完成后退出修改状态，即key1cnt=0.-Function: read DS1302 time, including hours and minutes, and send clock digital tube display
Key1, the realization of the cycle switch hours ten, an hour, ten minutes, a minute, exit settings and other functions when the switch to the corresponding bit, the corresponding bit flashing!
Key2: modify the corresponding time value, achieve 1 functions, according to the value of key1cnt, modify the corresponding bit, such as key1cnt=1, then modify the hours ten, and each press 1 times, the bit plus 1,
Key3: implementation of the change, the key2 set the hour minutes to write DS1302, modify the completion of the withdrawal the modified state, that is, key1cnt=0.
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Size: 4096 |
Author: lishoujun |
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Description: A VHDL pulse generator that generates customizable square wave pulses on an arbitrary number of channels. Controlled by UART communication through serial port. Tuned for 5ns period clock signal.
The pulse width and delay of each channel is fully adjustable through serial port while the design is running. Channels can also be turned on and off.
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Size: 17408 |
Author: Eugene |
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