Search - Convolutional encoder verilog

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[VHDL-FPGA-Verilog] crc_16 DL : 0: 利用verilog实现的一个（2,1,2）卷积码的编码器,很有用的哟!-Verilog realize the use of a (2,1,2) convolutional code encoder, yo useful!
Update : 2025-02-17 Size : 1kb Publisher : 刘横
[VHDL-FPGA-Verilog] viterbi DL : 0: 卷积码编码及其Viterbi译码的实现-Convolutional code encoder and Viterbi decoding to achieve
Update : 2025-02-17 Size : 250kb Publisher : mediative
[VHDL-FPGA-Verilog] interleaver DL : 0: 交织编码器的verilog代码实现，此外有testbench和波形。-the verilog code for the interleave encoder, with the testbench code and waveform screen print.
Update : 2025-02-17 Size : 63kb Publisher : Yang Jie
[VHDL-FPGA-Verilog] conv_encode DL : 0: 本设计是一个基于FPGA的咬尾卷积码编码器设计，要求使用verilog语言编写编码器模块，通过编译和综合，并通过matlab和modelsim仿真对比验证设计结果。-The design is an FPGA-based tail-biting convolutional code encoder design requires the use verilog language encoder module, through compilation and synthesis, and by contrast matlab and modelsim simulation results validate the design.
Update : 2025-02-17 Size : 18.69mb Publisher : 郭婷
[VHDL-FPGA-Verilog] conv_encoder DL : 0: TD-LTE中（3.1.7）咬尾卷积码编码器verilog代码-Tail-biting convolutional code encoder verilog code
Update : 2025-02-17 Size : 1kb Publisher : 杨总
[Com Port] tcm_enc DL : 0: 用Verilog实现（2,1,2）卷积码和8—PSk调制相结合的TCM编码器-Using Verilog realize (2,1,2) convolutional code and 8-PSk modulation encoder combination of TCM
Update : 2025-02-17 Size : 1kb Publisher : 程星
[VHDL-FPGA-Verilog] verilog-juanjima DL : 1: 卷积码是一种重要的前向纠错信道编码方式，其纠错性能常常优于分组码，且(2,1,7)卷积码已应用于现代卫星通信系统中。Viterbi译码算法能最大限度地发挥卷积码的优异性能。这里采用Verilog HDL语言设计出(2,1,7)卷积码的编码器模块和基于Viterbi算法的译码器模块，译码器采用全并行结构，译码速度快-Convolutional code is an important forward error correction channel coding method, and its error correction performance is often better than the block code, and (2,1,7) convolutional code has been used in modern satellite communication system. Viterbi decoding algorithm can maximize the performance of convolutional codes. Here is the Verilog HDL design (2,1,7) convolutional code encoder module and decoder module based on Viterbi algorithm, the decoder is designed using the parallel structure and the decoding speed is fast.
Update : 2025-02-17 Size : 10kb Publisher : 邓博于、