Description: 基于Verilog-HDL的硬件电路的实现
9.3 脉冲计数与显示
9.3.1 脉冲计数器的工作原理
9.3.2 计数模块的设计与实现
9.3.3 parameter的使用方法
9.3.4 repeat循环语句的使用方法
9.3.5 系统函数$random的使用方法
9.3.6 脉冲计数器的Verilog-HDL描述
9.3.7 特定脉冲序列的发生
9.3.8 脉冲计数器的硬件实现
-based on Verilog-HDL hardware Circuit of 9.3 pulse count and showed 9.3 .1 pulse counter the principle 9.3.2 Counting Module Design and Implementation para 9.3.3 meter usage 9.3.4 repeat cycle statement on the use 9.3.5- EC $ random function of the use of pulse counter 9.3.6 Verilog-HDL depiction 9.3.7 to specific pulse sequences occurred pulse counter 9.3.8 Hardware Implementation Platform: |
Size: 4096 |
Author:宁宁 |
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