Search - D flipflop

[VHDL-FPGA-Verilog] async_FlipFlop

Description: asynchronous D-FlipFlop & JK-FlipFlop.. with test bench.
Platform: | Size: 2048 | Author: harkirat | Hits:

[Software Engineering] part4

Description: d flipflop using verilog
Platform: | Size: 17408 | Author: atula136 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: vhdl program for d -flipflop with asynchronous reset
Platform: | Size: 31744 | Author: jenaipsita | Hits:

[VHDL-FPGA-Verilog] d_flip_175

Description: 4 D-FlipFlop source code with VHDL
Platform: | Size: 1024 | Author: micom76 | Hits:

[VHDL-FPGA-Verilog] dflipflop

Description: d flipflop for verilog code
Platform: | Size: 2048 | Author: mella | Hits:

[VHDL-FPGA-Verilog] D_flip

Description: source vhdl code of D flipflop logic
Platform: | Size: 12288 | Author: ahmad | Hits:

[VHDL-FPGA-Verilog] dff

Description: this the code for d flipflop -this is the code for d flipflop
Platform: | Size: 8192 | Author: nagaraju | Hits:

[Other Embeded program] success-128-switch-editing

Description: controlling D flipflop circuit
Platform: | Size: 62464 | Author: raj | Hits:

[Other] 17dynamic-edited

Description: dynamic d flipflop hspice model
Platform: | Size: 1024 | Author: renguoma | Hits:

[Software Engineering] d-flipflop

Description: D flip flop designing in ASIC
Platform: | Size: 2048 | Author: Shweta | Hits:

[VHDL-FPGA-Verilog] johncounter_D

Description: VHDL CODE FOR JOHNSON COUNTER USING D FLIPFLOP
Platform: | Size: 592896 | Author: pinky | Hits:

[Other] FlipFlipD

Description: FOR VLSI SIMUADOR OF A KIND D FLIPFLOP
Platform: | Size: 396288 | Author: flaper24 | Hits:

Description: In this paper, we describe two single input threshold gate (TLG) designs, which are functionally equivalent to differential flipflops. We present a detailed comparison of TLGs with two well established D-flipflop designs. The comparisons are done in both 65nm and 28nm commercial processes. We compare total delay, which is defined as the sum of setup delay and clock to output delay.We also show a comparison of tolerance against noise and process variation between the different designs. The two proposed designs are found to be as robust as an existing D-flipflop both commercial standard cell libraries. Meanwhile, they are 33 and 25 faster in 65nm post-layout and 25 and 22 faster in 28nm post-layout compared to a commercial D-flipflop.-In this paper, we describe two single input threshold gate (TLG) designs, which are functionally equivalent to differential flipflops. We present a detailed comparison of TLGs with two well established D-flipflop designs. The comparisons are done in both 65nm and 28nm commercial processes. We compare total delay, which is defined as the sum of setup delay and clock to output delay.We also show a comparison of tolerance against noise and process variation between the different designs. The two proposed designs are found to be as robust as an existing D-flipflop both commercial standard cell libraries. Meanwhile, they are 33 and 25 faster in 65nm post-layout and 25 and 22 faster in 28nm post-layout compared to a commercial D-flipflop.
Platform: | Size: 443392 | Author: salomi | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[VHDL-FPGA-Verilog] async_FlipFlop

[Software Engineering] part4

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] d_flip_175

[VHDL-FPGA-Verilog] dflipflop

[VHDL-FPGA-Verilog] D_flip

[VHDL-FPGA-Verilog] dff

[Other Embeded program] success-128-switch-editing

[Other] 17dynamic-edited

[Software Engineering] d-flipflop

[VHDL-FPGA-Verilog] johncounter_D

[Other] FlipFlipD

[JSP/Java] converted-(1)

[Software Engineering] code

[VHDL-FPGA-Verilog] DFlipflop

[VHDL-FPGA-Verilog] 2_FFs

[VHDL-FPGA-Verilog] New folder

CodeBus www.codebus.net