Search - D flipflop

Search - D flipflop - List

[VHDL-FPGA-Verilog] async_FlipFlop DL : 0: asynchronous D-FlipFlop & JK-FlipFlop.. with test bench.
Date : 2025-07-08 Size : 2kb User : harkirat
[Software Engineering] part4 DL : 0: d flipflop using verilog
Date : 2025-07-08 Size : 17kb User : atula136
[VHDL-FPGA-Verilog] vhdl DL : 0: vhdl program for d -flipflop with asynchronous reset
Date : 2025-07-08 Size : 31kb User : jenaipsita
[VHDL-FPGA-Verilog] d_flip_175 DL : 0: 4 D-FlipFlop source code with VHDL
Date : 2025-07-08 Size : 1kb User : micom76
[VHDL-FPGA-Verilog] dflipflop DL : 0: d flipflop for verilog code
Date : 2025-07-08 Size : 2kb User : mella
[VHDL-FPGA-Verilog] D_flip DL : 0: source vhdl code of D flipflop logic
Date : 2025-07-08 Size : 12kb User : ahmad
[VHDL-FPGA-Verilog] dff DL : 0: this the code for d flipflop -this is the code for d flipflop
Date : 2025-07-08 Size : 8kb User : nagaraju
[Other Embeded program] success-128-switch-editing DL : 0: controlling D flipflop circuit
Date : 2025-07-08 Size : 61kb User : raj
[Other] 17dynamic-edited DL : 0: dynamic d flipflop hspice model
Date : 2025-07-08 Size : 1kb User : renguoma
[Software Engineering] d-flipflop DL : 0: D flip flop designing in ASIC
Date : 2025-07-08 Size : 2kb User : Shweta
[VHDL-FPGA-Verilog] johncounter_D DL : 0: VHDL CODE FOR JOHNSON COUNTER USING D FLIPFLOP
Date : 2025-07-08 Size : 579kb User : pinky
[Other] FlipFlipD DL : 0: FOR VLSI SIMUADOR OF A KIND D FLIPFLOP
Date : 2025-07-08 Size : 387kb User : flaper24
[JSP/Java] converted-(1) DL : 0: In this paper, we describe two single input threshold gate (TLG) designs, which are functionally equivalent to differential flipflops. We present a detailed comparison of TLGs with two well established D-flipflop designs. The comparisons are done in both 65nm and 28nm commercial processes. We compare total delay, which is defined as the sum of setup delay and clock to output delay.We also show a comparison of tolerance against noise and process variation between the different designs. The two proposed designs are found to be as robust as an existing D-flipflop both commercial standard cell libraries. Meanwhile, they are 33 and 25 faster in 65nm post-layout and 25 and 22 faster in 28nm post-layout compared to a commercial D-flipflop.-In this paper, we describe two single input threshold gate (TLG) designs, which are functionally equivalent to differential flipflops. We present a detailed comparison of TLGs with two well established D-flipflop designs. The comparisons are done in both 65nm and 28nm commercial processes. We compare total delay, which is defined as the sum of setup delay and clock to output delay.We also show a comparison of tolerance against noise and process variation between the different designs. The two proposed designs are found to be as robust as an existing D-flipflop both commercial standard cell libraries. Meanwhile, they are 33 and 25 faster in 65nm post-layout and 25 and 22 faster in 28nm post-layout compared to a commercial D-flipflop.
Date : 2025-07-08 Size : 433kb User : salomi
[Software Engineering] code DL : 0: Basic codes in VHDL like d flipflop,register -Basic codes in VHDL like d flipflop,register ............
Date : 2025-07-08 Size : 1.5mb User : Uppu
[VHDL-FPGA-Verilog] DFlipflop DL : 0: Verilog Program for a d flipflop
Date : 2025-07-08 Size : 458kb User : tom
[VHDL-FPGA-Verilog] 2_FFs DL : 0: Flipflop with all possible combination verilog
Date : 2025-07-08 Size : 11kb User : mgvayada
[VHDL-FPGA-Verilog] New folder DL : 0: verilog codes for counter,d flipflop,fibonacci series,prime numbers,top.
Date : 2025-07-08 Size : 3kb User : sanh