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[Other resource] leon3-altera-ep2s60-ddr

Description: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Platform: | Size: 114780 | Author: king.xia | Hits:

[VHDL-FPGA-Verilog] Xilinx spartan 6 DDR 测试源代码

Description: Xilinx FPGA Spartan 6 上可运行的软核microblaze以及外设DDR, SPI,UART等测试代码
Platform: | Size: 18476664 | Author: jameszhou9019 | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl

Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Platform: | Size: 776192 | Author: 张涛 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: sdram控制器 这里考虑将SDRAM控制器结合目前项目开展来做相应的模块，而不做SDRAM通用控制器，这样也是考虑了FPGA的器件资源而采取的措施。同时编写的逻辑简单，没有多余的逻辑资源有利于提高控制器的速度，满足最后的设计要求。-SDRAM controller here consider SDRAM controller current projects do the corresponding module, but not so common SDRAM controller, as well as consider the FPGA device resources and the measures taken. While the preparation of simple logic, the logic is no spare resources to improve the speed controller to meet the final design requirements.
Platform: | Size: 3072 | Author: 林博 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_Controller

Description: DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
Platform: | Size: 677888 | Author: 钟方 | Hits:

[Other] xapp858[1]

Description: XAPP858 - 利用 Virtex-5 FPGA 实现的高性能 DDR2 SDRAM 接口数据采集 本应用指南描述了用于实现 667 Mbps（333 MHz）高性能 DDR2 SDRAM 接口的控制器和数据采集的技巧。 本数据采集技巧使用了输入串行器/解串器（ISERDES）和输出串行器/解串器（OSERDES）的功能。-XAPP858-use Virtex-5 FPGA high-performance DDR2 SDRA M Interface Data Acquisition Guide describes the application for achieving 667 Mbps (333 MHz) high-performance DDR 2 SDRAM Interface controller and data acquisition techniques. The data collection techniques used serial input/Solution Series (ISERDES) and serial output/Solution Series (O Legacy) function.
Platform: | Size: 296960 | Author: mingming | Hits:

[VHDL-FPGA-Verilog] ddr

Description: ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）
Platform: | Size: 1022976 | Author: yuling | Hits:

[VHDL-FPGA-Verilog] leon3-altera-ep2s60-ddr

Description: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy--adjust-vma=0x800000 output_file.hexout-O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Platform: | Size: 114688 | Author: | Hits:

[VHDL-FPGA-Verilog] ddr_ctrl

Description: verilog hdl coding DDR sdram control for fpga -verilog hdl coding DDR sdram control for fpga
Platform: | Size: 27648 | Author: 王郁 | Hits:

[Embeded-SCM Develop] DDRinterface

Description: 《ALTERA FPGA/CPLD高级篇》高速DDR存储器数据接口设计实例- ALTERA FPGA/CPLD High chapter high-speed DDR memory data interface design example
Platform: | Size: 24576 | Author: shicheng342 | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM

Description: 基于FPGA 实现DDR SDRAM的控制器-FPGA-based realization of DDR SDRAM controller
Platform: | Size: 474112 | Author: 张宁 | Hits:

[VHDL-FPGA-Verilog] rtl

Description: DDR控制器 已通过FPGA 验证 大家不要错过哦-DDR controller has passed FPGA to verify that we will not miss Oh
Platform: | Size: 52224 | Author: kin | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM

Description: 利用fpga读写ddr的源代码 实测可以使用-Ddr use FPGA to read and write the source code can use the measured
Platform: | Size: 474112 | Author: 朱宝军 | Hits:

[VHDL-FPGA-Verilog] c_xapp260

Description: xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Generator to simplify memory interface. This white paper discusses the various memory interface controller design challenges facing Warfare and Xilinx solutions, but also explains how to use Xilinx Software tools and hardware-proven reference designs to be for your own With (from low-cost DDR SDRAM applications to such as 667 Mb/s This higher performance DDR2 SDRAM interface) design a complete deposit Storage device interface solution.
Platform: | Size: 1123328 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] ddr_sdr_V1_1

Description: DDR控制器 - 用XILINX Virtex II FPGA实现 - 使用DDR MT46V16M16作为仿真模型 - 通用化-DR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted to any other DDR SDRAM device
Platform: | Size: 37888 | Author: jordanliang | Hits:

[VHDL-FPGA-Verilog] Twister_DDR_SDRAM_Board_Manual

Description: Twister DDR EP1C6Q240 FPGA 开发板 原理图，PCB,BOM-Twister Board Documentation Schematics, PCB and BOM Rev. B
Platform: | Size: 1452032 | Author: SEED | Hits:

[VHDL-FPGA-Verilog] FPGA-DDR-SDRA

Description: 基于FPGA 的DDR SDRAM高速数据采集的应用-DDR SDRAM high-speed FPGA-based data acquisition applications
Platform: | Size: 309248 | Author: 周勇 | Hits:

[VHDL-FPGA-Verilog] ddr

Description: 基于FPGA的ddr控制器的设计与实现，verilog，ISE-FPGA-based controller design and implementation of ddr, verilog, ISE
Platform: | Size: 179200 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilog] FPGA-SDRAM-control-code

Description: 该程序是FPGA控制DDR SRAM的控制源代码，使得SDRAM的控制变得简单。-This program is DDR SDRAM control code ,it makes the operation of SDRAM more easy.
Platform: | Size: 41984 | Author: didi | Hits:

[VHDL-FPGA-Verilog] DDR-SDRAM_IP_core

Description: DDR-SDRAM接口模块verilog源代码，可用作IP核使用，已在FPGA上验证-DDR-SDRAM interface module verilog source code, can be used as IP cores to use, proven
Platform: | Size: 474112 | Author: zyy | Hits:
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