Search - DDR SDRAM controller verilog

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[Other resource] very-good-ok-ref-ddr-sdram-verilog DL : 0: Sdr SDRAM控制器参考设计,很好的-Sdr SDRAM controller reference design, very good
Update : 2008-10-13 Size : 874.6kb Publisher : 姚明
[VHDL-FPGA-Verilog] ddr_verilog_xilinx DL : 0: DDR（双速率）SDRAM控制器参考设计，xilinx提供-DDR (double data rate) SDRAM controller reference design for Xilinx
Update : 2025-02-17 Size : 128kb Publisher : 陈旭
[VHDL-FPGA-Verilog] sdram DL : 0: sdram控制器这里考虑将SDRAM控制器结合目前项目开展来做相应的模块，而不做SDRAM通用控制器，这样也是考虑了FPGA的器件资源而采取的措施。同时编写的逻辑简单，没有多余的逻辑资源有利于提高控制器的速度，满足最后的设计要求。-SDRAM controller here consider SDRAM controller current projects do the corresponding module, but not so common SDRAM controller, as well as consider the FPGA device resources and the measures taken. While the preparation of simple logic, the logic is no spare resources to improve the speed controller to meet the final design requirements.
Update : 2025-02-17 Size : 3kb Publisher : 林博
[VHDL-FPGA-Verilog] very-good-ok-ref-ddr-sdram-verilog DL : 0: Sdr SDRAM控制器参考设计,很好的-Sdr SDRAM controller reference design, very good
Update : 2025-02-17 Size : 874kb Publisher : 姚明
[Software Engineering] DDR_SDRAM_controller_verilog DL : 0: DDR SRAM控制器的verilog完整设计文档（包含有完整的verilog源代码），-DDR SRAM controller complete Verilog design documents (including a complete Verilog source code),
Update : 2025-02-17 Size : 464kb Publisher : lipengfei
[VHDL-FPGA-Verilog] DDR_SDRAM_verilog DL : 0: DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的-DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good
Update : 2025-02-17 Size : 735kb Publisher : 宋珂
[VHDL-FPGA-Verilog] Xil3SD1800A_MIG_simplifiedUI_vlog_v92 DL : 0: verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
Update : 2025-02-17 Size : 887kb Publisher : ma yirong
[VHDL-FPGA-Verilog] ddr_verilog_xilinx DL : 0: xilinx的ddr sdram控制器文档-xilinx of ddr sdram controller documentation
Update : 2025-02-17 Size : 663kb Publisher : liujie
[VHDL-FPGA-Verilog] c_xapp260 DL : 0: xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Generator to simplify memory interface. This white paper discusses the various memory interface controller design challenges facing Warfare and Xilinx solutions, but also explains how to use Xilinx Software tools and hardware-proven reference designs to be for your own With (from low-cost DDR SDRAM applications to such as 667 Mb/s This higher performance DDR2 SDRAM interface) design a complete deposit Storage device interface solution.
Update : 2025-02-17 Size : 1.07mb Publisher : 陈阳
[VHDL-FPGA-Verilog] Altera_DDR_controller_core DL : 0: Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, description documents, DDR verilog model and simulation testbench are all included.
Update : 2025-02-17 Size : 735kb Publisher : 沈志
[VHDL-FPGA-Verilog] sdram_vhdl DL : 0: DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的。-DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good.
Update : 2025-02-17 Size : 871kb Publisher : 薛鹏展
[Windows Develop] DDR-SDRAM DL : 0: ddr sdram 控制器的源代码，内有vhdl和verilog。-DDR SDRAM controller
Update : 2025-02-17 Size : 882kb Publisher : 何海山
[VHDL-FPGA-Verilog] dab1814114c3 DL : 0: 此為採用ALTERA所做的DDR 控制器(verilog)- File/Directory Description ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation Contains the verilog testbench, modelsim project file, and library \source Contains the verilog source files for the DDR SDRAM reference design \synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
Update : 2025-02-17 Size : 860kb Publisher : 李志偉
[VHDL-FPGA-Verilog] DDR-SDRAM-controller-verilog-code DL : 0: DDR SDRAM控制器verilog代码及中文说明文档-DDR SDRAM controller verilog code and documentation
Update : 2025-02-17 Size : 477kb Publisher : 一样
[VHDL-FPGA-Verilog] DDR-SDRAM-Controller DL : 0: DDR SDRAM控制器verilog代码及中文说明文档-DDR SDRAM Controller Using Virtex-5 FPGA Devices
Update : 2025-02-17 Size : 256kb Publisher : 马龙
[Embeded-SCM Develop] DDR_MO DL : 0: 使用verilog语言实现简单的DDR SDRAM控制器(Using Verilog language to achieve a simple DDR SDRAM controller)
Update : 2025-02-17 Size : 1.05mb Publisher : 搬砖123