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[Embeded-SCM Develop] ref-ddr-sdram-verilog.zip DL : 0: sdram的verilog的源码实现
Update : 2025-02-17 Size : 882.5kb Publisher :
[Other resource] very-good-ok-ref-ddr-sdram-verilog DL : 0: Sdr SDRAM控制器参考设计,很好的-Sdr SDRAM controller reference design, very good
Update : 2008-10-13 Size : 874.6kb Publisher : 姚明
[VHDL-FPGA-Verilog] DDR（双速率）SDRAM控制器参考设计verilog代码 DL : 0: DDR SDRAM reference design documentation
Update : 2010-09-25 Size : 874.3kb Publisher : tony_gx@hotmail.com
[Embeded-SCM Develop] ref-ddr-sdram-verilog DL : 0: sdram的verilog的源码实现-sdram verilog source code realizes
Update : 2025-02-17 Size : 883kb Publisher : zfhustb
[VHDL-FPGA-Verilog] sdram DL : 0: sdram控制器这里考虑将SDRAM控制器结合目前项目开展来做相应的模块，而不做SDRAM通用控制器，这样也是考虑了FPGA的器件资源而采取的措施。同时编写的逻辑简单，没有多余的逻辑资源有利于提高控制器的速度，满足最后的设计要求。-SDRAM controller here consider SDRAM controller current projects do the corresponding module, but not so common SDRAM controller, as well as consider the FPGA device resources and the measures taken. While the preparation of simple logic, the logic is no spare resources to improve the speed controller to meet the final design requirements.
Update : 2025-02-17 Size : 3kb Publisher : 林博
[VHDL-FPGA-Verilog] very-good-ok-ref-ddr-sdram-verilog DL : 0: Sdr SDRAM控制器参考设计,很好的-Sdr SDRAM controller reference design, very good
Update : 2025-02-17 Size : 874kb Publisher : 姚明
[VHDL-FPGA-Verilog] DDRSDRAM DL : 0: DDR sdram 包含的完整的源码,仿真的相关文件-DDR sdram contains complete source code, simulation of the relevant documents
Update : 2025-02-17 Size : 998kb Publisher : 飞翔
[VHDL-FPGA-Verilog] ddr_ctrl DL : 0: verilog hdl coding DDR sdram control for fpga -verilog hdl coding DDR sdram control for fpga
Update : 2025-02-17 Size : 27kb Publisher : 王郁
[VHDL-FPGA-Verilog] sdram32 DL : 0: DDR SDRAM source verilog source codes
Update : 2025-02-17 Size : 25kb Publisher : sachin
[VHDL-FPGA-Verilog] ddr-sdram--chengxu DL : 0: ddr的控制程序，实用Verilog语言实现的非常的具体，非常无奈过的实用。-ddr
Update : 2025-02-17 Size : 14kb Publisher : 张杰
[VHDL-FPGA-Verilog] ddrsdram_verilog DL : 0: 内附doc是DDR SDRAM 参考设计文档；model包含SDRAM Verilog的模型；simulation包含verilog测试平台、modelsim工程文、设计库函数；source包含verilog源文件；synthesis包含工程的综合文件。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM Verilog model simulation with verilog test platform, modelsim project text, design library function source contains the verilog source files synthesis comprehensive document that contains the project.
Update : 2025-02-17 Size : 734kb Publisher : 陈少华
[VHDL-FPGA-Verilog] ddr-sdram DL : 0: DDR SDRAM控制器verilog代码及中文说明文档,对DDR开发很有用的哈。-Verilog source code for DDR SDRAM controler design,including guide book in chinese.
Update : 2025-02-17 Size : 902kb Publisher : runxin
[Other] ddr-sdram-verilog-resource DL : 0: 描述了ddr_sram的源代码,包括SDRAM的引脚功能介绍和Verilog在modulesim及quartus ii的实现-description the resource code of ddr_sram
Update : 2025-02-17 Size : 875kb Publisher : wangyuzhuo
[VHDL-FPGA-Verilog] ref-ddr-sdram-verilog DL : 0: ddr_sdram开发参考verilog建模-ddr_sdram with verilog
Update : 2025-02-17 Size : 736kb Publisher : pengyong
[VHDL-FPGA-Verilog] Altera_DDR_controller_core DL : 0: Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, description documents, DDR verilog model and simulation testbench are all included.
Update : 2025-02-17 Size : 735kb Publisher : 沈志
[VHDL-FPGA-Verilog] DDR-SDRAM_IP_core DL : 0: DDR-SDRAM接口模块verilog源代码，可用作IP核使用，已在FPGA上验证-DDR-SDRAM interface module verilog source code, can be used as IP cores to use, proven
Update : 2025-02-17 Size : 463kb Publisher : zyy
[Windows Develop] DDR-SDRAM DL : 0: ddr sdram 控制器的源代码，内有vhdl和verilog。-DDR SDRAM controller
Update : 2025-02-17 Size : 882kb Publisher : 何海山
[VHDL-FPGA-Verilog] DDR-SDRAM-controller-verilog-code DL : 0: DDR SDRAM控制器verilog代码及中文说明文档-DDR SDRAM controller verilog code and documentation
Update : 2025-02-17 Size : 477kb Publisher : 一样
[VHDL-FPGA-Verilog] verilog-ddr-sdram DL : 0: 用verilog实现的ddr sdram控制器-ddr sdram by verilog hdl
Update : 2025-02-17 Size : 735kb Publisher : 黄志沛
[Embeded-SCM Develop] DDR_MO DL : 0: 使用verilog语言实现简单的DDR SDRAM控制器(Using Verilog language to achieve a simple DDR SDRAM controller)
Update : 2025-02-17 Size : 1.05mb Publisher : 搬砖123

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