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[Other] ug_ddr_ddr2_sdram_hp.rar DL : 0: altera ddr2 user guid
Update : 2011-01-25 Size : 1.69mb Publisher : mcu031@163.com
[ARM-PowerPC-ColdFire-MIPS] Altera的IP源码8237 DL : 0: 名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持-renowned name of the company Synopsys 8051IP Core VHDL language, support can be keilC51
Update : 2025-02-17 Size : 203kb Publisher : 上面的
[VHDL-FPGA-Verilog] 1189152740 DL : 0: DDR2 SDRAM 控制器的FPGA实现-DDR2 SDRAM controller FPGA to achieve
Update : 2025-02-17 Size : 83kb Publisher : 白皓
[Other] ddr_ddr2_sdram9.0 DL : 0: altera 公司提供的ddr_ddr2_sdram9.0，DDR2 SDRAM 源代码-altera provided ddr_ddr2_sdram9.0, DDR2 SDRAM source code
Update : 2025-02-17 Size : 891kb Publisher : tiantian
[VHDL-FPGA-Verilog] DDR_SDRAMDesignTutorials DL : 0: Altera公司的基于NIOSII设计DDR和DDR2内存的资料，很有帮助的，-Based on Altera' s DDR and DDR2 memory NIOSII design information, useful,
Update : 2025-02-17 Size : 3.01mb Publisher : iyoung
[VHDL-FPGA-Verilog] ddr2_test DL : 0: 一个用Verilog写的DDR2的控制器（我们项目是在Altera的FPGA）成功仿真，并且使用到了项目中控制DDR2-A written using Verilog DDR2 controller (our project in Altera' s FPGA) successful simulation, and used to control the DDR2 in project
Update : 2025-02-17 Size : 10.37mb Publisher : 左洪成
[VHDL-FPGA-Verilog] DE3_User_manual DL : 0: ALtera公司的ED3开发板，用户手册，The DE3 board has plenty of features that allow users to implement a wide range of designed circuits.-The DE3 board has plenty of features that allow users to implement a wide range of designed circuits.The Stratix® III device is capable of dealing with resource consuming projects and complex algorithm verification, and the HSTC interface is provided for high-speed inter-connection and configurable I/O standards. The DDR2 SO-DIMM socket offers the opportunity of faster memory access experience, while the SD card socket provides the extension of data storage.
Update : 2025-02-17 Size : 4.99mb Publisher : leilei
[VHDL-FPGA-Verilog] c4gx_f896_host_ddr2a_odt DL : 0: ALTERA PCIE FPGA开发板（EP4C平台）DDR2内存测试代码-ALTERA PCIE FPGA development board (EP4C platform) DDR2 memory test code
Update : 2025-02-17 Size : 633kb Publisher : liyilang
[VHDL-FPGA-Verilog] test_ddr2_mem_model DL : 0: ddr2 test bench top for altera fpga.-ddr2 test bench top for fpga.
Update : 2025-02-17 Size : 4kb Publisher : ShengbingChou
[Communication] cdanpianji DL : 0: 红色飓风四代 altera DDR2 FPGA 开发 -FPGA development DDR2
Update : 2025-02-17 Size : 436kb Publisher : 高玉飞
[Software Engineering] ug_ddr_ddr2_sdram_hp DL : 0: ALTERA DDR2高性能控制器使用文档，包括存储控制器、用户接口、用户测试模块，各控制信号的说明。-ALTERA DDR2 high performance controller using a document, including the memory controller, user interface, user testing module, the control signal description.
Update : 2025-02-17 Size : 2.85mb Publisher : ft
[VHDL-FPGA-Verilog] ddr_ddr2_sdram-ip DL : 0: 该程序为Altera 公司 DDR DDR2 SDRAM 的IP源程序安装包，非常有价值的东西，借此网址共享下。-The program for Altera Corporation DDR DDR2 SDRAM of IP source installation package, a very valuable thing, whereby the URL Sharing.
Update : 2025-02-17 Size : 8.36mb Publisher : 刘明