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Description: DDR sdram 包含的完整的源码,仿真的相关文件
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Size: 1021984 |
Author: 飞翔 |
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Description: 基于FPGA 实现DDR SDRAM的控制器
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Size: 474402 |
Author: 张宁 |
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Description:
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Size: 415232 |
Author: auljdy |
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Description: DDR sdram 包含的完整的源码,仿真的相关文件-DDR sdram contains complete source code, simulation of the relevant documents
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Size: 1021952 |
Author: 飞翔 |
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Description: 基于FPGA 实现DDR SDRAM的控制器-FPGA-based realization of DDR SDRAM controller
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Size: 474112 |
Author: 张宁 |
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Description: DDR SDRAM的资料,有兴趣的朋友可以下下来-DDR SDRAM information, interested to see friends down under
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Size: 73728 |
Author: sy |
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Description: DDR SDRAM的veilog hdl程序,经过验证
效果不错-DDR SDRAM' s veilog hdl procedures, good results verified
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Size: 475136 |
Author: 寒心雪林 |
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Description: 基于Xilinx FPGA的DDRSDRAM的Verilog控制代码,使用的FPGA为Virtex-4,实现对DDRSDRAM的简单控制(对一系列地址的写入和读取)。-Xilinx FPGA-based DDRSDRAM the control of the Verilog code, the use of the FPGA for the Virtex-4, to achieve a simple DDRSDRAM control (on a series of addresses to write and read).
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Size: 477184 |
Author: 姜琰俊 |
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Description: DDR SDRAM设计及调试经验总结.pdf
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Size: 338944 |
Author: arens09 |
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Description: ddrsdram的中文说明书,很详细,对初学者很有用-ddr sdram
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Size: 417792 |
Author: 肖娟 |
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Description: 用vdhl编写的DDR sdram控制器,采用模块化编写,条理清楚,注解详细,附有存储器的说明。-the ddr sdram controller base vhdl
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Size: 476160 |
Author: tangjieling |
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Description: 适用于DDRSDRAM和DDR2SDRAM的控制器的设计-Applicable DDRSDRAM and DDR2SDRAM the controller design
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Size: 1977344 |
Author: alins |
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Description: HOW_TO_USE_DDR_SDRAM_-_User s_Manual.pdf
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Size: 473088 |
Author: Mike |
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Description: 一种DDRSDRAM通用测试电路的设计与实现A DDRSDRAM General Test Circuit Design and Implementation-A DDRSDRAM General Test Circuit Design and Implementation
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Size: 346112 |
Author: mylove75 |
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Description: 一个基于Xilinx FPGA的DDRSDRAM的Verilog控制代码,使用的FPGA为Virtex完整源代码。-A Xilinx FPGA-based control DDRSDRAM the Verilog code for the Virtex FPGA using the full source code.
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Size: 475136 |
Author: 召唤 |
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Description: implementation of ddrsdram
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Size: 6144 |
Author: steiner |
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Description: 基于Xilinx FPGA的DDRSDRAM的Verilogg控制代码,使用的FPGA为Virtex.
-Based on Xilinx FPGA' s DDRSDRAM Verilogg control code, the use of FPGA as the Virtex.
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Size: 478208 |
Author: ttian1000 |
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Description: 对ddrsdram操作,用VHDL语言实现,read,write的接口电路控制-Erase operation to read and write on the ddrsdram
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Size: 3072 |
Author: 王伯祥 |
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Description: 基于VHDL的DDR SDRAM控制器的设计,实现数据的读写功能,迸发长度分为2,4,8-Based on the VHDL DDR SDRAM controller design, implementation of data read and write capabilities, burst into the length of 2, 4, 8
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Size: 823296 |
Author: zhangjiefei |
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Description: 一个ddrsdram时序约束文件的例子,对于fpga新手来说,是个不错的参考学习的资料-Example of of a ddrsdram timing constraints file, for fpga novice, is a good reference for learning the information
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Size: 4096 |
Author: 钱雪荣 |
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