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[VHDL-FPGA-Verilog] DDS小数分频 DL : 0: 文件列表(点击判断是否您需要的文件，如果是垃圾请在下面评价投诉): DDS小数分频 ...........\Block1.vhd.bak ...........\db ...........\..\add_sub_9mh.tdf ...........\..\DDS.asm.qmsg ...........\..\DDS.asm_labs.ddb ...........\..\DDS.cbx.xml ...........\..\DDS.cmp.bpm ...........\..\DDS.cmp.cdb ...........\..\DDS.cmp.ecobp ...........\..\DDS.cmp.hdb ...........\..\DDS.cmp.logdb ...........\..\DDS.cmp.rdb ...........\..\DDS.cmp.tdb ...........\..\DDS.cmp0.ddb ...........\..\DDS.cmp2.ddb ...........\..\DDS.cmp_bb.cdb ...........\..\DDS.cmp_bb.hdb ...........\..\DDS.cmp_bb.logdb ...........\..\DDS.cmp_bb.rcf ...........\..\DDS.dbp ...........\..\DDS.db_info ...........\..\DDS.eco.cdb ...........\..\DDS.eds_overflow ...........\..\DDS.fit.qmsg ...........\..\DDS.fnsim.cdb ...........\..\DDS.fnsim.hdb ...........\..\DDS.fnsim.qmsg ...........\..\DDS.hier_info ...........\..\DDS.hif ...........\..\DDS.map.bpm ...........\..\DDS.map.cdb ...........\..\DDS.map.ecobp ...........\..\DDS.map.hdb ...........\..\DDS.map.logdb ...........\..\DDS.map.qmsg ...........\..\DDS.map_bb.cdb ...........\..\DDS.map_bb.hdb ...........\..\DDS.map_bb.logdb ...........\..\DDS.pre_map.cdb ...........\..\DDS.pre_map.hdb ...........\..\DDS.psp ...........\..\DDS.pss ...........\..\DDS.rtlv.hdb ...........\..\DDS.rtlv_sg.cdb ...........\..\DDS.rtlv_sg_swap.cdb ...........\..\DDS.sgdiff.cdb ...........\..\DDS.sgdiff.hdb ...........\..\DDS.signalprobe.cdb ...........\..\DDS.sim.cvwf ...........\..\DDS.sim.hdb ...........\..\DDS.sim.qmsg ...........\..\DDS.sim.rdb ...........\..\DDS.sld_design_entry.sci ...........\..\DDS.sld_design_entry_dsc.sci ...........\..\DDS.syn_hier_info ...........\..\DDS.tan.qmsg ...........\..\prev_cmp_DDS.asm.qmsg ...........\..\prev_cmp_DDS.fit.qmsg ...........\..\prev_cmp_DDS.map.qmsg ...........\..\prev_cmp_DDS.sim.qmsg ...........\..\prev_cmp_DDS.tan.qmsg ...........\..\wed.wsf ...........\DDS.asm.rpt ...........\DDS.bdf ...........\DDS.done ...........\DDS.dpf ...........\DDS.fit.rpt ...........\DDS.fit.smsg ...........\DDS.fit.summary ...........\DDS.flow.rpt ...........\DDS.map.rpt ...........\DDS.map.summary ...........\DDS.pin ...........\DDS.pof ...........\DDS.qpf ...........\DDS.qsf ...........\DDS.sim.rpt ...........\DDS.sof ...........\DDS.tan.rpt ...........\DDS.tan.summary ...........\DDS.vhd ...........\DDS.vhd.bak ...........\DDS.vwf ...........\lpm_add_sub0.bsf ...........\lpm_add_sub0.inc ...........\lpm_add_sub0.tdf ...........\lpm_add_sub0_waveforms.html ...........\lpm_add_sub1.bsf ...........\lpm_add_sub1.inc ...........\lpm_add_sub1.tdf ...........\lpm_add_sub1_waveforms.html ...........\lpm_add_sub2.bsf ...........\lpm_add_sub2.inc ...........\lpm_add_sub2.tdf ...........\lpm_add_sub2_waveforms.html ...........\parallel_add0.bsf
Date : 2009-05-03 Size : 495.98kb User : beijbinghe@163.com
[Books] dds DL : 0: 直接数字频率合成器dds资料-Direct Digital Frequency Synthesizer dds information
Date : 2025-07-06 Size : 890kb User : 易小弟
[VHDL-FPGA-Verilog] dds正弦发生器代码 DL : 0: 讲述了dds直接数字频率合成的基本原理，同时用ＶＨＤＬ语言编写dds原代码用于生成正弦波，并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果-described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for simulation and verification MATLAB sine wave output
Date : 2025-07-06 Size : 480kb User : czy
[SCM] DDS数字信号发生器 DL : 0: DDS数字信号发生器,采用AD9835DDS 专用芯片输出范围1K--10MHZ 采用X25045作看门狗及数据存储器，用于设置各项参数的存储内含电路图，源程序及一些相关资料-DDS digital signal generator, using AD9835DDS ASIC output range 1K-- Knoxville watchdog for the use of X25045 and data memory, used to set various parameters of storage containing circuit, the source and related information
Date : 2025-07-06 Size : 2.12mb User : 董庆
[Communication-Mobile] DDS+PLL DL : 0: 基于FPGA的新的DDS+PLL时钟发生器-FPGA-based new DDS PLL clock generator
Date : 2025-07-06 Size : 142kb User : 李敏
[VHDL-FPGA-Verilog] dds-design DL : 0: * DESCRIPTION: DDS design BY PLD DEVICES. * * AUTHOR: Sun Yu * * HISTORY: 12/06/2002 *-* DESCRIPTION : DDS BY PLD design Online.** AUTHOR : Sun Yu** HISTORY : 12/06/2002*
Date : 2025-07-06 Size : 1kb User : 魏杰
[Communication] Project1-DDS DL : 0: 直接频率和成DDS，可以在Altera的FPGA下载实现-directly into DDS frequency and can be downloaded from Altera FPGA Implementation
Date : 2025-07-06 Size : 8kb User : lf
[VHDL-FPGA-Verilog] dds-design DL : 0: DDS design with vhdl language.
Date : 2025-07-06 Size : 1kb User :
[SCM] AD9851-dds DL : 0: AD9851-dds的设计资料，原代码和原理图-AD9851- dds of design data, source code and the schematic diagram
Date : 2025-07-06 Size : 4kb User : 鲁军波
[SCM] DDS+51 DL : 0: 本程序功能: DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-this program functions : DDS folder procedures, complete direct digital frequency synthesis, sine, triangle, Three square waveform, and can sweep. can be set up through the keyboard operation frequency waveform parameters and the types of choice and control operations. composed of two parts, "C" folder, for the 51 microcontroller running C Programming Language, "Verilog" folder, use the Verilog language FPGA procedures.
Date : 2025-07-06 Size : 1003kb User : 吴健
[SCM] DDS DL : 0: 基于ｆｐｇａ，采用ｑｕａｒｔｕｓ２的ＤＤＳ信号发生器，采用高速ＤＡＣ９０８为数模芯片，并可通过５１单片机送入调制信号进行ＦＭ调制-Based on the fpga, the use of the DDS signal generator quartus2 using DAC908 number of high-speed chip module, and passed into 51 single-chip FM modulation signal modulation
Date : 2025-07-06 Size : 2.62mb User : 张新
[Other] DDS DL : 0: 详细介绍DDS的基本工作原理，并给出实际中常用的几款芯片的使用方法。-DDS detailed introduction of the basic working principle, and gives several commonly used in the actual use of the chip.
Date : 2025-07-06 Size : 1.08mb User : 夕阳
[VHDL-FPGA-Verilog] dds DL : 0: 用FPGA实现DDS,可变频,幅值由硬件完成-Using FPGA realize DDS, can be frequency, amplitude from hardware to complete
Date : 2025-07-06 Size : 659kb User : liuyu
[Other] DDS DL : 0: dds->9954的pcb供大家参考,这个扳子我调通了的可以放心开办-dds-
Date : 2025-07-06 Size : 68kb User : kblost
[SCM] FPGA--DDS-PhaseMeasure DL : 0: Verilog实现的DDS正弦信号发生器和测频测相模块，DDS模块可产生两路频率和相位差均可预置调整的值正弦波，频率范围为20Hz-5MHz，相位范围为0°-359°，测量的数据通过引脚传输给单片机，单片机进行计算和显示。-Verilog realize the DDS sine wave signal generator and frequency measurement module test phase, DDS module can generate both frequency and phase difference can be preset to adjust the value of sine wave, frequency range of 20Hz-5MHz, phase range of 0 °-359 ° , measurement data and transmit them to the single-chip pin, single-chip microcomputer to calculate and display.
Date : 2025-07-06 Size : 1.31mb User : haoren
[SCM] 3co---dds DL : 0: 直接数字频率合成（DDS）程序,使用adc9851芯片-Direct Digital Synthesis (DDS), the use of chip adc9851
Date : 2025-07-06 Size : 1kb User : zhao onely
[Other] dds DL : 0: 基于DDS的高性能信号源的设计是pdf格式的哦-DDS-based high-performance signal source is designed to be Oh pdf format
Date : 2025-07-06 Size : 293kb User : whhit911
[VHDL-FPGA-Verilog] DDS-2 DL : 0: 用FPGA实现DDS的原理图，结构清晰，采用总线方式与外部单片机通信-FPGA realization of DDS with the schematic diagram, structural clarity, the use of bus-way communication with the outside Singlechip
Date : 2025-07-06 Size : 13kb User : 赵培立
[ARM-PowerPC-ColdFire-MIPS] dds DL : 0: 此为基于ARM7编写的,采用周立功LPC2131系列ARM编写,用的是C语言,实现的是DDS AD9850 正弦波产生,晶振(参考频率)为PWM6产生,外围电路参照有关电路,不管何总都一样.-This is prepared based on the ARM7, the LPC2131 series ARM Ligong weeks to prepare, using the C language, realize that the DDS AD9850 sine wave generation, crystal (reference frequency) to produce PWM6 external circuit with reference to the relevant circuit, regardless of the total HE are the same.
Date : 2025-07-06 Size : 158kb User : shijiqian
[VHDL-FPGA-Verilog] DDS DL : 0: 用51和 FPGA实现的 DDS的程序-FPGA with 51 and realize the process of DDS
Date : 2025-07-06 Size : 5kb User : 胡玉贵

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