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[VHDL-FPGA-Verilog] DDS_VHDL_xzy

Description: 在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器，芯片是Altera公司的-in EDA software development QuartusII use VHDL DDS signal generator , chip companies are Altera
Platform: | Size: 4760576 | Author: xiaoyong | Hits:

[VHDL-FPGA-Verilog] dds

Description: 直接数字频率合成器，基于vhdl语言，在qartus II上实现，下载调试成功-Direct digital frequency synthesizer, based on the VHDL language, in qartus II achieved a successful download debugging
Platform: | Size: 316416 | Author: 浮云 | Hits:

[Software Engineering] 07_DDSmokuai

Description: DDS模块 EWB Quartus2编译 电子综合设计试验箱程序-DDS module EWB Quartus2 chamber compile electronic integrated design process
Platform: | Size: 75776 | Author: 罗健 | Hits:

[VHDL-FPGA-Verilog] learn_dds

Description: 基于quartus ii 9.0的简易dds波形发生器，可以产生正弦，方波，三角波，可变幅，可变频。非常适合学习使用，使用时请按自己的芯片和引脚设置-Quartus ii 9.0 Based on dds simple waveform generator can produce sine, square, triangle wave can be amplitude, frequency can be. Very suitable for learning to use, when used by their chip and pin set
Platform: | Size: 732160 | Author: 陈东旭 | Hits:

[VHDL-FPGA-Verilog] DDS_100325(13)_success

Description: QUARTUS II环境下VHDL语言编写DDS程序，双数字信号输出，一为正弦波幅值输出，一正弦波差值信号。时钟2^21HZ，带24bits频率控制字。-QUARTUS II environment, VHDL language DDS program, two digital signal output, an amplitude for the sine wave output, a sine wave difference signal. Clock 2 ^ 21HZ, with 24bits frequency control word.
Platform: | Size: 1087488 | Author: 骆东君 | Hits:

[VHDL-FPGA-Verilog] BPSK

Description: 在quartus ii下完成的用VHDL语言编写的数字式调频BPSK的调制，其中DDS和成型滤波使用ip核完成-Accomplished in quartus ii the use of VHDL language digital FM BPSK modulation, which use the ip filter DDS and forming complete nuclear
Platform: | Size: 326656 | Author: | Hits:

[VHDL-FPGA-Verilog] ep1c12_29_dds

Description: DDS设计：该程序完成了在Quartus Ⅱ上使用VHDL语言实现的DDS波形调制设计-DDS Design: The procedure is completed in Quartus ii the DDS waveform modulation design using VHDL language
Platform: | Size: 494592 | Author: 无敌县令 | Hits:

[Communication] DDS

Description: 基于DDS原理，利用VHDL语言进行正弦波、三角波、锯齿波、矩形波等波形的发生。包括完整代码和QUARTUS II工程。-Based on DDS principle, the use of VHDL, sine, triangle, sawtooth, square wave waveform occurs. Including the complete code and QUARTUS II project.
Platform: | Size: 147456 | Author: chuangfen | Hits:

[VHDL-FPGA-Verilog] DDSN

Description: quartus II 13.0 DDS工程文件，采用VHDL编写，可输出正交两路正弦信号。可以直接用modelsim-alter 仿真-quartus II 13.0 DDS project file, using VHDL written two orthogonal sinusoidal output signals. Can be simulated directly modelsim-alter
Platform: | Size: 1873920 | Author: 连天 | Hits:

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