Search - DDS vhdl

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[VHDL-FPGA-Verilog] dds正弦发生器代码 DL : 0: 讲述了dds直接数字频率合成的基本原理，同时用ＶＨＤＬ语言编写dds原代码用于生成正弦波，并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果-described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for simulation and verification MATLAB sine wave output
Update : 2025-02-17 Size : 480kb Publisher : czy
[VHDL-FPGA-Verilog] ddsVHDL DL : 0: 基于VHDL的DDS设计，在QUTURS2zhon仿真通过-based on the DDS VHDL design and simulation through the QUTURS2zhon
Update : 2025-02-17 Size : 95kb Publisher : wl
[Communication] Project1-DDS DL : 0: 直接频率和成DDS，可以在Altera的FPGA下载实现-directly into DDS frequency and can be downloaded from Altera FPGA Implementation
Update : 2025-02-17 Size : 8kb Publisher : lf
[VHDL-FPGA-Verilog] dds-design DL : 0: DDS design with vhdl language.
Update : 2025-02-17 Size : 1kb Publisher :
[VHDL-FPGA-Verilog] DDSsingal DL : 0: 三相直接数字频率合成器dds的VHDL源码，希望对大家有帮助-three-phase direct digital frequency synthesizers dds VHDL source code, we hope to help
Update : 2025-02-17 Size : 17kb Publisher : xingyang
[VHDL-FPGA-Verilog] DDS DL : 0: 用51和 FPGA实现的 DDS的程序-FPGA with 51 and realize the process of DDS
Update : 2025-02-17 Size : 5kb Publisher : 胡玉贵
[Communication-Mobile] DDS DL : 0: DDS的VHDL源代码，是数字QPSK调制解调中的重要组成部分。-DDS of the VHDL source code, the number of QPSK modulation and demodulation is an important part.
Update : 2025-02-17 Size : 3kb Publisher :
[VHDL-FPGA-Verilog] VHDL DL : 0: 一个直接数字频率合成的查表程序,VHDL语言,使用7128调试通过-A direct digital frequency synthesis of look-up table procedures, VHDL language, using 7128 debugging through
Update : 2025-02-17 Size : 144kb Publisher : Chen.Y.M
[SCM] dds DL : 0: 课程设计-DDS 很好,能够很好实现功能-Curriculum design-DDS good, able to realize a good functional
Update : 2025-02-17 Size : 3kb Publisher : 洋气
[VHDL-FPGA-Verilog] DDs DL : 0: 这是我的毕业设计，是用VHDL编程的直接扩频发生器。-This is my graduation project is the use of VHDL programming direct spread-spectrum generator.
Update : 2025-02-17 Size : 449kb Publisher : shengm1
[VHDL-FPGA-Verilog] vhdl DL : 0: vhdl的一些源代码，包括dds 设计，交通灯设计，信号发生器设计的一些源代码-Some of VHDL source code, including dds design, traffic signal design, signal generator designed a number of source code
Update : 2025-02-17 Size : 69kb Publisher : 马斌
[VHDL-FPGA-Verilog] dds DL : 0: 直接数字频率合成器，基于vhdl语言，在qartus II上实现，下载调试成功-Direct digital frequency synthesizer, based on the VHDL language, in qartus II achieved a successful download debugging
Update : 2025-02-17 Size : 309kb Publisher : 浮云
[VHDL-FPGA-Verilog] dds DL : 0: 基于CYCLONE II的程序,DDS原理的函数信号发生器.采用查表法实现.各位可以参考.-CYCLONE II based on the procedure, DDS Function Generator principle. Realize the use of look-up table method. Members may refer to.
Update : 2025-02-17 Size : 226kb Publisher : Yin
[Other Embeded program] DDS DL : 0: 基于DDS的数字移相正弦信号发生器设计，EDA技术在全国大学生电子设计竞赛中的应用-DDS-based digital phase-shifting sinusoidal signal generator design, EDA Technology in the National Undergraduate Electronic Design Contest Application
Update : 2025-02-17 Size : 217kb Publisher : Alex
[VHDL-FPGA-Verilog] dds DL : 0: DDS正弦信号发生器频率和相位连续可调。频率最大2M
Update : 2025-02-17 Size : 3kb Publisher : dsf
[VHDL-FPGA-Verilog] dds DL : 0: DDs直接数字频率合成器的源代码，其中包括采用IP核和普通两种方式-DDS Direct Digital Synthesizer source code, including the use of IP core and the general two ways
Update : 2025-02-17 Size : 1.31mb Publisher : 谭儆轩
[VHDL-FPGA-Verilog] dds DL : 0: 利用fpga实现的DDS，可输出正弦波，输出频率可调-FPGA realization of the use of DDS, sine wave output, output frequency adjustable
Update : 2025-02-17 Size : 458kb Publisher : qlg
[VHDL-FPGA-Verilog] dds DL : 0: 实现dds功能，利用quartus软件，子模块包括加法器，锁相环，date-rom 利用原图将各模块综合，利用ps2键盘控制频率及相位。-Dds realize functions, using Quartus software, sub-modules including the adder, phase-locked loop, date-rom image to the module using integrated, using ps2 keyboard to control the frequency and phase.
Update : 2025-02-17 Size : 2.72mb Publisher : lijingfeng
[VHDL-FPGA-Verilog] vhdl-dds DL : 0: fpga 控制dds 程序。希望对各位有用-dds FPGA control procedures. Members wish to be useful
Update : 2025-02-17 Size : 86kb Publisher : martin
[VHDL-FPGA-Verilog] DDS DL : 0: DDS调试心得,VERIOLG 各HDL和VHDL语言的DDS调试方法-DDS debugging experience, VERIOLG the HDL and VHDL languages DDS debugging method
Update : 2025-02-17 Size : 52kb Publisher : 李达兴

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