Search - DDS vhdl code

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[VHDL-FPGA-Verilog] FPGA_SUM99_VHDL_SOURCE DL : 0: 基于FPGA的直接数字合成器的设计与分析的代码程序,代码格式为VHDL-FPGA-based Direct Digital Synthesis Design and Analysis of the code procedures for VHDL code format
Update : 2025-03-15 Size : 5kb Publisher : 莫汉伟
[VHDL-FPGA-Verilog] dds_quicklogic DL : 1: 高手写的VHDL源码，实现DDS跳频器功能请大家多提意见-experts write VHDL source code, the frequency-hopping DDS functionality Please speak up
Update : 2025-03-15 Size : 25kb Publisher : duyi
[VHDL-FPGA-Verilog] ddsmatlab DL : 0: dds在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-dds dspbuilder under the VHDL source code and test incentives document matl ab model, the simulation under through modelsim
Update : 2025-03-15 Size : 6kb Publisher : zqh
[VHDL-FPGA-Verilog] DDSsingal DL : 0: 三相直接数字频率合成器dds的VHDL源码，希望对大家有帮助-three-phase direct digital frequency synthesizers dds VHDL source code, we hope to help
Update : 2025-03-15 Size : 17kb Publisher : xingyang
[VHDL-FPGA-Verilog] DDS DL : 0: 用51和 FPGA实现的 DDS的程序-FPGA with 51 and realize the process of DDS
Update : 2025-03-15 Size : 5kb Publisher : 胡玉贵
[Communication-Mobile] DDS DL : 0: DDS的VHDL源代码，是数字QPSK调制解调中的重要组成部分。-DDS of the VHDL source code, the number of QPSK modulation and demodulation is an important part.
Update : 2025-03-15 Size : 3kb Publisher :
[VHDL-FPGA-Verilog] VHDL DL : 0: 一个直接数字频率合成的查表程序,VHDL语言,使用7128调试通过-A direct digital frequency synthesis of look-up table procedures, VHDL language, using 7128 debugging through
Update : 2025-03-15 Size : 144kb Publisher : Chen.Y.M
[VHDL-FPGA-Verilog] vhdl DL : 0: vhdl的一些源代码，包括dds 设计，交通灯设计，信号发生器设计的一些源代码-Some of VHDL source code, including dds design, traffic signal design, signal generator designed a number of source code
Update : 2025-03-15 Size : 69kb Publisher : 马斌
[VHDL-FPGA-Verilog] dds DL : 0: DDs直接数字频率合成器的源代码，其中包括采用IP核和普通两种方式-DDS Direct Digital Synthesizer source code, including the use of IP core and the general two ways
Update : 2025-03-15 Size : 1.31mb Publisher : 谭儆轩
[Embeded-SCM Develop] 200741691252 DL : 0: dds源代码，vhdl程序，函数信号发生器。-dds source code, vhdl procedure, function signal generator.
Update : 2025-03-15 Size : 4kb Publisher : 吴飞
[VHDL-FPGA-Verilog] dds DL : 0: 使用VHDL硬件描述语言实现了直接频率合成器的制作，并在Altera公司的CycloneII上得到实现，验证了代码的正确性。用户操作可以参照程序中的说明，请使用QuartusII6.0以上版本打开，低版本打开时会有错误提示-Using VHDL hardware description language to achieve a direct frequency synthesizer production, and Altera s CycloneII be realized, to verify the correctness of the code. Users can refer to procedures, please use the above QuartusII6.0 open, low-version will be opened error
Update : 2025-03-15 Size : 103kb Publisher : xx
[VHDL-FPGA-Verilog] DDS DL : 0: 实现函数波形发生器的功能，内有用自己编的源代码实现的，也有用quartus的IP核实现的。-The realization of the function waveform generator function, useful for their own realization of the source code, it also uses the IP core quartus achieved.
Update : 2025-03-15 Size : 1.19mb Publisher : bluesky428
[VHDL-FPGA-Verilog] FPGA-DDS DL : 1: 在FPGA内，以查表方式实现频率直接合成器（DDS）功能。verilog源代码-In the FPGA in order to achieve the look-up table means the direct synthesizer frequency (DDS) feature. verilog source code
Update : 2025-03-15 Size : 2kb Publisher : niuqs
[VHDL-FPGA-Verilog] DDS DL : 0: 本代码可以用于产生正余弦信号波形，利用FPGA内部的ROM放置一个正余弦采样点的数据表格，通过循环取址的方法，实现波形连续输出。-This code can be used to generate positive cosine signal waveforms, using FPGA' s internal ROM to place a sampling point is the cosine of the data tables, the circulation method of taking the site to achieve a continuous output waveform.
Update : 2025-03-15 Size : 473kb Publisher : 蔡野锋
[Other] DDS DL : 0: 这个一个基于FPGA的DDS原代码可以生成正弦和余弦两种波形-This is a DDS code bepend on FPGA ,it can generate two waves.
Update : 2025-03-15 Size : 9kb Publisher : wuyanjun
[VHDL-FPGA-Verilog] 8psk DL : 0: 利用DDS原理设计8psk的原代码，已通过调试-8psk principle design using DDS source code, which has passed the commissioning
Update : 2025-03-15 Size : 1.72mb Publisher : luyuan
[VHDL-FPGA-Verilog] DDS DL : 0: DDS数字频率合成的verilog代码，附有正余弦查找表等-DDS digital frequency synthesis verilog code, with a cosine look-up table, etc.
Update : 2025-03-15 Size : 16mb Publisher : allen-haha
[VHDL-FPGA-Verilog] singnal DL : 0: VHDL实现通用通信信号源，包括sin，cos，方波，三角波，BPSK，GMSK，ASK，16QAM等信号的产生以及DDS，PLL的VHDL系统代码-VHDL implementation of universal communication sources, including sin, cos, square, triangle, BPSK, GMSK, ASK, 16QAM and other signal generation and DDS, PLL system, the VHDL code
Update : 2025-03-15 Size : 1kb Publisher : 张泽端
[VHDL-FPGA-Verilog] DDS DL : 0: 这个是在quartusii和matlab simulink下搭的dds的模型，已经经过仿真是可以的。并且已经转为vhdl代码。-This is quartusii and matlab simulink model to catch the dds, has been the simulation is possible. And has to vhdl code.
Update : 2025-03-15 Size : 1.23mb Publisher : jiang
[VHDL-FPGA-Verilog] dds DL : 0: VHDL的DDS代码，也就是直接数字式频率合成器设计-The DDS VHDL code, which is Direct Digital Frequency Synthesizer
Update : 2025-03-15 Size : 3kb Publisher : quanguoxiang

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