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[Communication] DDS_VERILOG

Description: 本例给出了DDS的VERIOG的程序事例,可发生正弦\\余弦等波形,适应与通信方面的硬件实现!-the cases presented DDS VERIOG procedures example, can occur sine \\ cosine wave such as, Adaptation and communications hardware realization!
Platform: | Size: 3309 | Author: 陈榧 | Hits:

[Communication] DDS_VERILOG

Description: 本例给出了DDS的VERIOG的程序事例,可发生正弦\余弦等波形,适应与通信方面的硬件实现!-the cases presented DDS VERIOG procedures example, can occur sine \ cosine wave such as, Adaptation and communications hardware realization!
Platform: | Size: 3072 | Author: 陈榧 | Hits:

[SCM] DDS_VERILOG

Description: 超级精简的DDS发生器，用VERILOG编写，请参考-Super-streamlined DDS generator with VERILOG preparation, please refer to
Platform: | Size: 3072 | Author: 吴宏伟 | Hits:

[VHDL-FPGA-Verilog] DDS_VERILOG

Description: verilog dds 在发生正弦波时，很好的参考代码-verilog dds
Platform: | Size: 3072 | Author: 王洋 | Hits:

[VHDL-FPGA-Verilog] DDS_verilog

Description: 通讯中常用的dds模块的verilog源码打包下载-Communications commonly used in dds module verilog source code package to download
Platform: | Size: 609280 | Author: sofia | Hits:

[VHDL-FPGA-Verilog] DDS_verilog

Description: 采用verilog实现了DDS发生器，源码已通过仿真编译已经板级调试，可直接模块化使用。-Verilog achieved using the DDS generator, source code has been compiled by board-level simulation debugging, modularity can be directly used.
Platform: | Size: 2048 | Author: 杨安娜 | Hits:

[VHDL-FPGA-Verilog] dds_verilog

Description: 产生信号发生器的dds的verilog代码，很好的学习资料，值得学习-Verilog code generated signal generator dds good learning materials, it is worth learning
Platform: | Size: 3072 | Author: 李军 | Hits:

[File Format] dds_verilog

Description: 学习dds的FPGA程序。对学习fpga的朋友是很好的帮助-Learning ddsFPGA program. Of the learning fpga friend is a good help
Platform: | Size: 7168 | Author: hehe | Hits:

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