Search - DE2 pin

[SCM] DE2_pin_assignments

Description: altera DE2开发板的管脚配置文件很好用的哦-altera DE2 development board of the pin configuration files used by Oh well
Platform: | Size: 2048 | Author: chxinrui | Hits:

[VHDL-FPGA-Verilog] DE2_70_pin_assignments

Description: de2-70的引脚配置文件，给各位急需分享一下，用于fpga的开发-de2-70 of the pin configuration files, to share that much-needed for the development of fpga
Platform: | Size: 3072 | Author: 朱轶凌 | Hits:

Description: 简单的7段数码管驱动，对应de2，可直接用，内含de2板子的管脚分配-Simple digital control driver 7, corresponding to de2, can be directly used, containing de2 board pin allocation
Platform: | Size: 608256 | Author: 袁野 | Hits:

[VHDL-FPGA-Verilog] DE2usingbook

Description: DE2中文用户手册，方便查找各引脚所对的编码-DE2 Chinese user manual, easy to find the pin that on the coding
Platform: | Size: 5675008 | Author: xtp | Hits:

[Software Engineering] piny_DE2

Description: Pin on Altera DE2 Board
Platform: | Size: 187392 | Author: bart | Hits:

[VHDL-FPGA-Verilog] DE2jieshao

Description: DE2中文用户手册。对de2板的各个模块的一些介绍和管脚图-DE2 Chinese user manual. De2 board of some description of each module and the pin map
Platform: | Size: 5675008 | Author: lutangshi | Hits:

[VHDL-FPGA-Verilog] DE2EP2C35F672

Description: DE2 EP2C35F672d的管脚分配图-DE2 EP2C35F672d pin allocation map
Platform: | Size: 16384 | Author: 浩然 | Hits:

[VHDL-FPGA-Verilog] codelock7(0)

Description: Altera的DE2板子的一个简易密码锁，引脚信号已经引入，在实验板上调试通过-Altera' s DE2 board a simple password lock pin has been introduced by the experimental board debugging
Platform: | Size: 2286592 | Author: zxy | Hits:

[Embeded-SCM Develop] lab1

Description: 本实验主要练习使用Quartus II 9.1软件进行简单的FPGA 的I/O口实验，实验使用的是DE2开发板，使用芯片为EP2C35F672C6。本次实验的重点是掌握Quartus II 进行系统设计的流程、方法及调试技巧，并对DE2开发板的各个引脚的含义及使用有所了解。-This experiment and practice using the Quartus II 9.1 software is a simple FPGA' s I/O port experiments using a DE2 development board, using the chip EP2C35F672C6. The focus of this experiment is to master the Quartus II design flow, methods, and debugging techniques, and each pin DE2 development board understand the meaning and use.
Platform: | Size: 586752 | Author: xjnkasndx | Hits:

[VHDL-FPGA-Verilog] DE2-VGA-LED

Description: verilog HDL 语言编写的，FPGA的数码管和VGA的显示。调用时不必修改源码，只需引脚映射对就可以-verilog HDL language, FPGA digital and VGA display. Call without having to modify source code, you can just pin on the map
Platform: | Size: 5793792 | Author: | Hits:

[VHDL-FPGA-Verilog] DE2_pin_assignments

Description: DE2_pin_assignments DE2开发板引脚设置-DE2_pin_assignments DE2 development board pin
Platform: | Size: 2048 | Author: 林培豪 | Hits:

[VHDL-FPGA-Verilog] SEG7

Description: ALTERA公司DE2开发板的数码管驱动程序，包含引脚配置文件-ALTERA DE2 board digital driver contains the pin configuration files
Platform: | Size: 371712 | Author: LX | Hits:

[VHDL-FPGA-Verilog] DE2_115_PS2_DEMO

Description: DE2-115开发板上的PS2针口程序，VHDL语言开发，QT2环境下可调式-PS2 pin port program the DE2-115 development board, VHDL language development, QT1 environment adjustable
Platform: | Size: 217088 | Author: 杨平平 | Hits:

[Program doc] DE2-board-of-pin

Description: 有关de2开发板的管教分配，以及应用问题！-The distribution of discipline related to the the de2 development board, as well as the problem!
Platform: | Size: 68608 | Author: wang | Hits:

[ARM-PowerPC-ColdFire-MIPS] DE2_NIOS

Description: DE2 板子的范例内涵引脚连接示范硬件配置和大量常用IP CORE 非常适合新手学习研究-Example content of the DE2 board demonstration hardware configuration and a large number of commonly used IP CORE pin is ideal for the novice to learn research
Platform: | Size: 1746944 | Author: wang | Hits:

[VHDL-FPGA-Verilog] DE2_70_pin_assignments

Description: DE2-70开发板中附带的引脚的分配列表，格式为.csv的-DE2-70 development board comes with the pin assignment list, in the format. Csv
Platform: | Size: 4096 | Author: boyzone | Hits:

[Compress-Decompress algrithms] frequency-counter

Description: 这是用verilog写的配合DE2 FPGA开发板的10进制显示频率计的工程文件夹的压缩包，解压后可直接下载到DE2板上，其中频率输入端是系统自带27M时钟D13用于测试，如果想要应用于别的开发板，可以重新分配引脚。-DE2 FPGA development board with with verilog write with decimal display frequency meter project folder compression package, after decompression can be directly downloaded to the DE2 board, in which the frequency of the input of the system comes with 27M clock D13 used for testing If you want to apply to other development board can reassign pin.
Platform: | Size: 615424 | Author: 予烨 | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: DE2 SDRAM Controller Pin Configuration Set-DE2 SDRAM Controller Pin Configuration Set!!!
Platform: | Size: 1224704 | Author: choi | Hits:

[VHDL-FPGA-Verilog] Quartus_FPGA

Description: this a smal programme that convert a binary code to a gray code, and a file that expalin the DE2 pin assignements-this is a smal programme that convert a binary code to a gray code, and a file that expalin the DE2 pin assignements
Platform: | Size: 154624 | Author: takachy | Hits:

[VHDL-FPGA-Verilog] DE2-115引脚分配

Description: DE2-115引脚分配说明，使用时查找十分方便。(DE2-115 pin assignment description)
Platform: | Size: 28672 | Author: MGGM | Hits:

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[SCM] DE2_pin_assignments

[VHDL-FPGA-Verilog] DE2_70_pin_assignments

[VHDL-FPGA-Verilog] LEDtest

[VHDL-FPGA-Verilog] DE2usingbook

[Software Engineering] piny_DE2

[VHDL-FPGA-Verilog] DE2jieshao

[VHDL-FPGA-Verilog] DE2EP2C35F672

[VHDL-FPGA-Verilog] codelock7(0)

[Embeded-SCM Develop] lab1

[VHDL-FPGA-Verilog] DE2-VGA-LED

[VHDL-FPGA-Verilog] DE2_pin_assignments

[VHDL-FPGA-Verilog] SEG7

[VHDL-FPGA-Verilog] DE2_115_PS2_DEMO

[Program doc] DE2-board-of-pin

[ARM-PowerPC-ColdFire-MIPS] DE2_NIOS

[VHDL-FPGA-Verilog] DE2_70_pin_assignments

[Compress-Decompress algrithms] frequency-counter

[VHDL-FPGA-Verilog] SDRAM

[VHDL-FPGA-Verilog] Quartus_FPGA

[VHDL-FPGA-Verilog] DE2-115引脚分配

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