Search - DECADE COUNTER

[VHDL-FPGA-Verilog] daima

Description: 用VHDL语言设计一个数字秒表： 1、秒表的计时范围是0秒~59分59.99秒，显示的最长时间为59分59秒。 2、计时精度为10MS。 3、复位开关可以随时使用，按下一次复位开关，计时器清零。 4、具有开始/停止功能，按一下开关，计时器开始计时，再按一下，停止计时。系统设计分为几大部分，包括控制模块、时基分频模块、计时模块和显示模块等。其中，计时模块有分为六进制和十进制计时器。计时是对标准时钟脉冲计数。计数器由四个十进制计数器和两个六进制计数器构成，其中毫秒位、十毫秒位、秒位和分位用十进制计数器，十秒位和十分位用六进制计数器。计时显示电路时将计时值在LED上七段数码管上显示出来。计时电路产生的计时值经过BCD七段码后，驱动LED数码管。-With VHDL language design digit stopwatch: 1, Stopwatch s time scope is 0 second ~59 minute 59.99 second, the demonstration longest time is 59 minute 59 second. 2, The time precision is 10MS. 3, The reset switch may momentarily use, presses down a reset switch, the timer reset. 4, Has starts/the stop function, according to the switch, the timer starts to time, presses again, stops timing. The system design divides into several major parts, including control module, time base frequency division module, time module and display module and so on. And, the time module influentials for the senary and the decimal base timer. The time is to the standard clock pulse counting. Counter by four decade counters and two senary counter constitution, a millisecond position, ten milliseconds positions, a second position and the rank with the decade counter, ten second position and ten ranks use the senary counter. When time display circuit will time the value on the nixietube to demonstrate on LED. The
Platform: | Size: 5120 | Author: SAM | Hits:

[VHDL-FPGA-Verilog] DECADE

Description: Decade Counter in VHDL using Xilinx tool
Platform: | Size: 576512 | Author: dhiraj | Hits:

[Other Embeded program] mm

Description: this file is function decade counter
Platform: | Size: 3072 | Author: kashif | Hits:

[VHDL-FPGA-Verilog] mod10asynchro

Description: this is a verilog code for asynchronous mod-10 counter.its also called a decade counter.
Platform: | Size: 23552 | Author: swapna | Hits:

[SCM] cascade4017

Description: Shows how to cascade 4017 counter.Helps beginers in the use of 4017 decade counters.
Platform: | Size: 18432 | Author: Fidelhi | Hits:

[VHDL-FPGA-Verilog] counter

Description: 六十进制计数器，自动进位，有点小错，实在改不过来了-Six-decade counter, automatic bit, a little wrong, but it changed to a
Platform: | Size: 2048 | Author: 王一 | Hits:

[VHDL-FPGA-Verilog] running_light_schamatic_

Description: circuit diagramm is lunning light(led) with ic cd 4017 decade counter and -circuit diagramm is lunning light(led) with ic cd 4017 decade counter and 555
Platform: | Size: 4096 | Author: dinu | Hits:

[assembly language] design-a-decade-counter

Description: 设计一个四位二进制计数器，将计数结果由数码管显示，显示结果为十进制数。数码管选通为低电平有效，段码为高电平有效。-The design of a four-bit binary counter will count digital display, and displays the results as a decimal number. Digital tube strobe active-low segment code for active high.
Platform: | Size: 15360 | Author: jingzai | Hits:

[assembly language] VHDL

Description: 74LS161 JK触发器带清0端,项目名称为dff_JK_111 十进制计数器74LS290,项目名定为CTLS290：运算方法编写的290计数器：另一种编法LS290 不带使能端的3线8线译码器八选一数具选择器：用CASE语句全加器：简单的JK触发器-74LS161 JK flip-flop with cleared end Project Name dff_JK_111 decade counter 74LS290 project name as CTLS290: and computing method for the preparation of the 290 counter: Another compilation Act LS290 8 line decoder can end line without eight JK flip-flop election with a number of selector: full adder CASE statement:
Platform: | Size: 7168 | Author: Lynn | Hits:

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[VHDL-FPGA-Verilog] daima

[VHDL-FPGA-Verilog] DECADE

[Other Embeded program] mm

[VHDL-FPGA-Verilog] mod10asynchro

[SCM] cascade4017

[VHDL-FPGA-Verilog] counter

[VHDL-FPGA-Verilog] running_light_schamatic_

[assembly language] design-a-decade-counter

[assembly language] VHDL

[VHDL-FPGA-Verilog] Decade-Counter

[MiddleWare] Decade-Counter

[VHDL-FPGA-Verilog] counter

[VHDL-FPGA-Verilog] tt

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