Location:
Search - DES HDL
Search list
Description: HDL实现的DES算法,及相关的Test bench激励文件-HDL achieve the DES algorithm, and the related documents incentive Test bench
Platform: |
Size: 27710 |
Author: zyx |
Hits:
Description: fir ISP design
fir VHDL VHDL编程滤波的硬件描述语言实现,包括VHDL语言和verilog语言-fir fir VHDL design ISP programming VHDL hardware description of the filter language , including the VHDL language and verilog
Platform: |
Size: 112640 |
Author: xiong |
Hits:
Description: HDL实现的DES算法,及相关的Test bench激励文件-HDL achieve the DES algorithm, and the related documents incentive Test bench
Platform: |
Size: 27648 |
Author: zyx |
Hits:
Description: 包中包括,
DW8051完整的Verilog HDL代码
两本手册:
DesignWare Library DW8051 MacroCell, Datasheet
DesignWare DW8051 MacroCell Databook
三篇51论文:
基于IP 核的PSTN 短消息终端SoC 软硬件协同设计
Embedded TCP/ IP Chip Based on DW8051 Core
以8051为核的SOC中的万年历的设计 -DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!
Platform: |
Size: 1588224 |
Author: myfingerhurt |
Hits:
Description: 用HDL实现的DES加密算法,通过前仿真,希望对大家有帮助-HDL implementation of the DES with the encryption algorithm, by pre-simulation, we want to help
Platform: |
Size: 27648 |
Author: su |
Hits:
Description: DES加密算法的Verilog HDL实现,带模式选择端口,可以实现加密和解密,已经modelsim仿真通过。-Des En/Decrypt,Verilog HDL code
Platform: |
Size: 8192 |
Author: Amazing_Eric |
Hits:
Description: a triple-DES (Data Encryption Standard) hardware description in verilog-HDL with testbench
Platform: |
Size: 861184 |
Author: Farzad |
Hits:
Description: 用FPGA实现的DES和3DES算法,使用开发板DE2-115通过验证-EDS&3DES based on ALTERA-FPGA,realized by Verilog HDL and DE2-115board.
Platform: |
Size: 20877312 |
Author: 李刚 |
Hits:
Description: des代码,using verilog HDL,方便I使用(des code, using by verilog HDL.)
Platform: |
Size: 5120 |
Author: binbinlee
|
Hits: