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[VHDL-FPGA-Verilog] DES加密算法的VHDL实现 DL : 0: DES加密算法的VHDL实现,采用流水线技术
Update : 2009-05-14 Size : 16.9mb Publisher : rungiw
[Crack Hack] rom_des DL : 0: DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。-VHDL and VERILOG sourcecode and TESTBENCH of DES encrypting algorithm
Update : 2025-02-17 Size : 30kb Publisher :
[VHDL-FPGA-Verilog] DES DL : 0: DES　加密算法的实现，使用硬件描述语言VHDL编写-DES encryption algorithm realization, uses hardware description language VHDL to compile
Update : 2025-02-17 Size : 23kb Publisher : zfhustb
[VHDL-FPGA-Verilog] tcdg.vhdl DL : 0: des vhld 源码　程序完成了DES的编码和解码功能-des vhld source procedures completed DES encoding and decoding
Update : 2025-02-17 Size : 5kb Publisher : 王亮
[VHDL-FPGA-Verilog] hiervhdl DL : 0: Using Hierarchy in VHDL Design vhdl语言初学者的天堂-Using VHDL Design VHDL language beginners paradise
Update : 2025-02-17 Size : 43kb Publisher : 土木文田
[VHDL-FPGA-Verilog] des.tar DL : 0: 这是一个vhdl的 DES编程软件,希望大家喜欢 -This is a VHDL programming software DES hope you like
Update : 2025-02-17 Size : 37kb Publisher : 沈鹏
[VHDL-FPGA-Verilog] AEScoremodules DL : 0: AES decoder aes_dec.vhdl AES encoder aes_enc.vhdl Package used by rest of design aes_pkg.vhdl Key Expansion component for AES encoder and decoder key_expansion.vhdl -AES AES encoder decoder aes_dec.vhdl aes_ enc.vhdl Package used by rest of design aes_pkg . vhdl Key Expansion component for a AES encoder nd decoder key_expansion.vhdl
Update : 2025-02-17 Size : 10kb Publisher : 许茹芸
[Crack Hack] 3des-VHDL DL : 0: 3des的VHDL实现，适用于quartus环境-3des VHDL applicable to the environment quartus
Update : 2025-02-17 Size : 93kb Publisher : xin
[Crack Hack] des DL : 0: DES加密VHDL源代码,包括速度优先与面积优先两种设计-DES encrypted VHDL source code, including the rate of priority and an area of priority two design
Update : 2025-02-17 Size : 3.55mb Publisher : wlzpudn
[VHDL-FPGA-Verilog] vhdl DL : 0: This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examp terms of basic logic gates, to more complex systems, such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using any synthesised using current synthesis tools. -This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The exampterms of basic logic gates, to more complex systems, such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using anysynthesised using current synthesis tools.
Update : 2025-02-17 Size : 169kb Publisher : gbj
[VHDL-FPGA-Verilog] 3des_vhdl DL : 0: 3重DES（3DES）加密算法的问答及其VHDL实现。-3 re-DES (3DES) encryption algorithm and the Q
Update : 2025-02-17 Size : 137kb Publisher : 张开文
[Crack Hack] CODE DL : 0: DES encryption for verilog program
Update : 2025-02-17 Size : 9kb Publisher : socketa
[Crack Hack] mos_des DL : 0: 这是一个用VHDL语言实现了DES加密功能的程序，由于DES加密的模式，解密时需把密要倒置-This is a VHDL language with the DES encryption process, as a result of the mode of DES encryption, decryption is required to close to the inverted
Update : 2025-02-17 Size : 27kb Publisher : liyajun
[VHDL-FPGA-Verilog] DES DL : 0: DES算法的FPGA实现希望能有用。-DES algorithm can be useful to achieve the desired FPGA
Update : 2025-02-17 Size : 390kb Publisher : house2
[VHDL-FPGA-Verilog] des DL : 0: this is des code of vhdl version.
Update : 2025-02-17 Size : 3kb Publisher : bluedkdk
[VHDL-FPGA-Verilog] DES DL : 0: DES加密算法的VHDL实现,采用流水线技术实现-The VHDL implement of DES encrypt algorithmic
Update : 2025-02-17 Size : 16.9mb Publisher : Mr Yang
[VHDL-FPGA-Verilog] DES-HDL DL : 0: 用HDL实现的DES加密算法，通过前仿真，希望对大家有帮助-HDL implementation of the DES with the encryption algorithm, by pre-simulation, we want to help
Update : 2025-02-17 Size : 27kb Publisher : su
[VHDL-FPGA-Verilog] des DL : 0: des解密加密的verilog源代码其中包含有测试源代码，仿真结果图-verilog des decrypt encrypted source code which includes testing the source code, Simulation results
Update : 2025-02-17 Size : 335kb Publisher : cong
[VHDL-FPGA-Verilog] des DL : 0: VHDL实现的DES密码算法的完整的加解密。-DES
Update : 2025-02-17 Size : 7kb Publisher : duzhibo
[VHDL-FPGA-Verilog] DES DL : 0: 主要是一个DES加密程序，用VHDL语言进行开发实现-no
Update : 2025-02-17 Size : 4kb Publisher : sfds

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