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[VHDL-FPGA-Verilog] hiervhdl

Description: Using Hierarchy in VHDL Design vhdl语言初学者的天堂-Using VHDL Design VHDL language beginners paradise
Platform: | Size: 44032 | Author: 土木文田 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examp terms of basic logic gates, to more complex systems, such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using any synthesised using current synthesis tools. -This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The exampterms of basic logic gates, to more complex systems, such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using anysynthesised using current synthesis tools.
Platform: | Size: 173056 | Author: gbj | Hits:

[matlab] DESHTM

Description: 用VHDL语言实现了DES加密算法，其中包含了测试程序，能够进行仿真。-Using VHDL language implementation of the DES encryption algorithm, which contains the test procedures can be simulated.
Platform: | Size: 9216 | Author: 心飞扬 | Hits:

[VHDL-FPGA-Verilog] DES

Description: DES加密算法的VHDL实现,采用流水线技术实现-The VHDL implement of DES encrypt algorithmic
Platform: | Size: 17718272 | Author: Mr Yang | Hits:

[VHDL-FPGA-Verilog] key

Description: 用vhdl语言实现des编码中的密钥产生 是des编码中重要的一部分-Des code using vhdl language in the key generation is an important part des coding
Platform: | Size: 1024 | Author: guosai | Hits:

[Crack Hack] DES_16keys

Description: 用VC生成DES加解密算法的16轮密钥， 可直接用于编写DES的VHDL的密钥生成模块 -Generated using DES encryption and decryption algorithm VC 16-round keys can be directly used to write the VHDL DES key generation module
Platform: | Size: 1024 | Author: zhuangyan | Hits:

[VHDL-FPGA-Verilog] Description-of-DES-with-VHDL

Description: 用VHDL描述DES算法 用硬件的方式DES加解密 体现了硬件编程人一般思想-DES algorithm using VHDL description of the way with hardware DES encryption and decryption hardware programming reflects the general thinking of people
Platform: | Size: 14336 | Author: lichen | Hits:

[VHDL-FPGA-Verilog] SIMULATION-AND-SYNTHESIS-OF-TRIPLE-DES-BLOCK-CIPH

Description: SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL
Platform: | Size: 11264 | Author: saipraveen | Hits:

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