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[VHDL-FPGA-Verilog] divide

Description: 除法器的设计本文所采用的除法原理是：对于八位无符号被除数A，先对A转换成高八位是0低八位是A的数C，在时钟脉冲的每个上升沿C 向左移动一位，最后一位补零，同时判断C的高八位是否大于除数B，如是则C的高八位减去B，同时进行移位操作，将C的第二位置1。否则，继续移位操作。经过八个周期后，所得到的C的高八位为余数，第八位为商。从图(1)可清楚地看出此除法器的工作原理。此除法器主要包括比较器、减法器、移位器、控制器等模块。-Divider design used in this paper, the principle of division is: For the eight unsigned dividend A, the first of A into the high-low 8 0 8 is the A number of C, in each clock rising edge to the left C Mobile One, and finally a zero, at the same time to determine whether C is greater than the high-8 divisor B, so is the high C 8 minus B, at the same time shift operation, the location will be C s second one. Otherwise, continue to shift operation. After eight cycles, received a high C for more than eight the number of eighth place for the business. From Figure (1) can clearly see that the divider works. This mainly includes divider comparators, subtraction, and shifter, controller modules.
Platform: | Size: 1024 | Author: lyy | Hits:

[MPI] vhd_divider

Description: lattice isplever7竟然没有除法库,只好在网上找了老外写的vhdl除法器-lattice isplever7 Treasury did not divide, so the Internet to find a foreigner to write the VHDL divider
Platform: | Size: 6144 | Author: guyh | Hits:

[VHDL-FPGA-Verilog] divide

Description: 除法器-Divider
Platform: | Size: 2048 | Author: wangzhide | Hits:

[Algorithm] cordic

Description: cordic methods describe essentially the same algorithm that with suitably chosen inputs can be used to calculate a whole range of scientific functions including sin, cos, tan, arctan, arcsin, arccos, sinh, cosh, tanh, arctanh, log, exp, square root and even multiply and divide. the method dates back to volder [1959], and due to its versatility and compactness, it made possible the microcoding of the hp35 pocket scientific calculator in 1972. here is some code to illustrate the techniques. ive split the methods into three parts linear, circular and hyperbolic. in the hp35 microcode these would be unified into one function (for space reasons). because the linear mode can perform multiply and divide, you only need add/subtract and shift to complete the implementation. you can select in the code whether to do the multiples and divides also by cordic means. other multiplies and divides are all powers of 2 (these dont count). to eliminate these too, would involve ieee hackery.-cordic methods describe essentially the same algorithm that with suitably chosen inputs can be used to calculate a whole range of scientific functions including sin, cos, tan, arctan, arcsin, arccos, sinh, cosh, tanh, arctanh, log, exp, square root and even multiply and divide. the method dates back to volder [1959], and due to its versatility and compactness, it made possible the microcoding of the hp35 pocket scientific calculator in 1972. here is some code to illustrate the techniques. ive split the methods into three parts linear, circular and hyperbolic. in the hp35 microcode these would be unified into one function (for space reasons). because the linear mode can perform multiply and divide, you only need add/subtract and shift to complete the implementation. you can select in the code whether to do the multiples and divides also by cordic means. other multiplies and divides are all powers of 2 (these dont count). to eliminate these too, would involve ieee hackery.
Platform: | Size: 2048 | Author: waqas | Hits:

[Multimedia program] CLK_DIV

Description: 爱用硬件描述语言VHDL实现输入时钟10分频输出-divide CLOCK by 10 using VHDL
Platform: | Size: 3072 | Author: 陈绪文 | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 用VHDL语言设计简单的CPU，重点设计微操作代码，然后设计CPU各组成模块，最后根据设计的微操作设计微指令，验证设计的正确性。可基本实现加、减、乘、除、移位、循环等操作。-VHDL language is designed to be simple to use the CPU, the focus of the design of micro-operation code, and then design the components of CPU module designed the final design of the micro-operation microinstruction to verify the correctness of the design. Can achieve the basic add, subtract, multiply, divide, transfer, recycling and other operations.
Platform: | Size: 1268736 | Author: Rachel | Hits:

[Other] f

Description: This documents describes a free single precision floating point unit. This floating point unit can perform add, subtract, multiply, divide, integer to floating point and floating point to integer conversion.-This documents describes a free single precision floating point unit. This floating point unit can perform add, subtract, multiply, divide, integer to floating point and floating point to integer conversion.
Platform: | Size: 73728 | Author: k | Hits:

[VHDL-FPGA-Verilog] VHDLfenpin

Description: VHDL进行分频的完备资料,包含偶数、奇数、小数、分数-VHDL for the completeness of the information divide, including even and odd numbers, decimals, fraction
Platform: | Size: 322560 | Author: djbyy | Hits:

[Other] clk_div

Description: 分频计数器verilog源代码,包括实验说明文档,清晰易懂.-this code can easily be understood and teaches you how to divide the clock.
Platform: | Size: 199680 | Author: 颜爱良 | Hits:

[VHDL-FPGA-Verilog] VHDLcodes

Description: Behavioral description of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.- Behavioral description of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.
Platform: | Size: 6144 | Author: Vijay | Hits:

[VHDL-FPGA-Verilog] exercicio4

Description: VHDL program. Calculator that do basic operations. Add, subtract, divide and multiplication using Cyclone -VHDL program. Calculator that do basic operations. Add, subtract, divide and multiplication using Cyclone II
Platform: | Size: 1024 | Author: Ferdinando | Hits:

[Software Engineering] GeneratingFPGA-AcceleratedDFTLibraries

Description: 关于DFT的文章，应用FPGA实现傅立叶变换。-Abstract—We present a domain-specific approach to generate high-performance hardware-software partitioned implementations of the discrete Fourier transform (DFT). The partitioning strategy is a heuristic based on the DFT’s divide-and-conquer algorithmic structure and fine tuned by the feedback-driven exploration of candidate designs. We have integrated this approach in the Spiral linear-transform code-generation framework to support push-button automatic implementation. We present evaluations of hardware-software DFT implementations running on the embedded PowerPC processor and the reconfigurable fabric of the Xilinx Virtex-II Pro FPGA. In our experiments, the 1D and 2D DFT’s FPGA-accelerated libraries exhibit between 2 and 7.5 times higher performance (operations per second) and up to 2.5 times better energy efficiency (operations per Joule) than the software-only version.
Platform: | Size: 235520 | Author: 李然 | Hits:

[Other] jianyijisuanqiVHDL

Description: 用VHDL写的简易计算器，包括加减乘除，除法器用加法器和乘法器组成-Write simple calculator with VHDL, division, including add, subtract, multiply and divide adder on time-multiplier and used
Platform: | Size: 1018880 | Author: 倪萍波 | Hits:

[VHDL-FPGA-Verilog] The-way-of-divide-and-hex

Description: 这个文件中介绍了分频和各种进制编写的几种方法，VHDL语言，-This file is described in several sub-frequency and a variety of hex write the VHDL language,
Platform: | Size: 2048 | Author: 朱振军 | Hits:

[VHDL-FPGA-Verilog] 1M

Description: 一分频的VHDL程序，内容介绍非常详细，希望能给大家带来方便，很实用的-Divide the VHDL program, introduced in great detail, and the hope that they can bring convenience to very practical
Platform: | Size: 1024 | Author: 王龙飞 | Hits:

[VHDL-FPGA-Verilog] VHDL-counter

Description: 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号时非常重要的。 下面我们介绍分频器的VHDL描述，在源代码中完成对时钟信号CLK的2分频，4分频，8分频，16分频。 -In digital circuits, and often need high frequency clock divider operating in lower frequency clock signal. We know that when the clock signal in the hardware circuit design is very important. Here we introduce the VHDL description of the divider in the source code of the clock signal CLK divided by 2, 4 divider, divide by 8, divided by 16.
Platform: | Size: 86016 | Author: zhanghua | Hits:

[VHDL-FPGA-Verilog] VHDL-divider-design

Description: VHDL分频器设计，本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。-VHDL divider design, this article describes use cases, including even divide, non-50 duty cycle and 50 duty cycle odd divider, half integer (N+0-crossover design using VHDL for FPGA/CPLD .5) divider, fractional, fractional divider and integral divider.
Platform: | Size: 320512 | Author: 黄玲 | Hits:

[Books] divide

Description: 在ise 上设计8位除法器，并用modelsim仿真的vhdl代码-8 divider ise on design simulation with modelsim vhdl code
Platform: | Size: 2048 | Author: lin | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 正弦波发生器代码VHDL 其中包括分频 正弦波数据-Sine wave generator VHDL code Divide the sine wave data including
Platform: | Size: 7168 | Author: 123456789 | Hits:

[VHDL-FPGA-Verilog] Prescaler-to-use-VHDL-design

Description: 本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设计，包括偶数分频、非 50 占空比和50 占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使用的电路，并在 ModelSim 上进行验证。-This paper describes the use of examples prescaler to use VHDL design on FPGA/CPLD, including even frequency, non-50 duty cycle and 50 duty cycle odd frequency, half-integer (N+0.5) Divide, fractional, fractional and integral crossover frequency. All can be achieved through Synplify Pro FPGA synthesizer manufacturer or integrated to form a circuit that can be used and verified in ModelSim.
Platform: | Size: 339968 | Author: liufei | Hits:
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