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[Documents] 基于FPGA实现的PCIE协议的DMA读写模块 DL : 2: Update : 2011-05-05 Size : 513.43kb Publisher : 283386843@qq.com
[VHDL-FPGA-Verilog] eluosi_game DL : 0: 这是一个基于NIOSII的俄罗斯方块游戏设计，是基于FPGA的，利用流模式DMA传输实现游戏。-This is a box based on the Russian NIOSII game design, is based on the FPGA, and the use of streaming mode DMA transfer realize the game.
Update : 2025-02-17 Size : 8.16mb Publisher : 木易
[Embeded-SCM Develop] vgac_sst160aN DL : 0: 基于fpga和sopc的用VHDL语言编写的EDA的32位Nios CPU嵌入式系统及其DMA设计俄罗斯方块游戏机-FPGA and SOPC based on the use of VHDL language EDA 32-bit Nios CPU and the DMA design of embedded systems Tetris game
Update : 2025-02-17 Size : 2.09mb Publisher : 多幅撒
[VHDL-FPGA-Verilog] PCMCIACPLD DL : 0: 基于Samsung2410平台的PCMCIA中的DMA测试程序和Wait程序，还有经编译后的CPLD参数。-PCMCIA-based platform Samsung2410 the DMA test procedures and Wait procedures, as well as compiled by the CPLD parameters.
Update : 2025-02-17 Size : 14kb Publisher : 星梦
[VHDL-FPGA-Verilog] msp430_jtag_nios DL : 0: 将msp430与使用nios的fpga相连，将fpga作为msp430的jtag使用。其中用到了nios内的多种接口以及dma操作-The MSP430 with the use of the Nios FPGA connected to the FPGA as the MSP430 JTAG to use. Which used the Nios multiple interfaces and dma operation
Update : 2025-02-17 Size : 55kb Publisher : danielmu
[ARM-PowerPC-ColdFire-MIPS] NiosII_example DL : 0: FPGA中niosII的应用实例－－包括PIO，UART，DMA，ISR等的应用，比较基础，适合初学者比较透彻理解NiosII的应用-FPGA application in niosII- including PIO, UART, DMA, ISR and other applications, basis of comparison, suitable for beginners relatively thorough understanding of the application of NiosII
Update : 2025-02-17 Size : 8kb Publisher : 刘彩苗
[VHDL-FPGA-Verilog] C20_sram_vga DL : 0: FPGA应用如sd卡控制，led控制，vga音频控制-Sd card FPGA applications such as control, led control, vga audio control
Update : 2025-02-17 Size : 1.46mb Publisher : 钟灶生
[Linux-Unix] Linux_bc DL : 0: 对vga接口做了详细的介绍，并且有一 ·三段式Verilog的IDE程序，但只有DMA ·电子密码锁，基于fpga实现，密码正 ·IIR、FIR、FFT各模块程序设计例程， ·基于逻辑工具的以太网开发，基于逻 ·自己写的一个测温元件（ds18b20）的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example（McGr ·这是CAN总线控制器的IP核，源码是由 ·FPGA设计的SDRAM控制器，有仿真代码 ·xilinx fpga 下的IDE控制器原代码, ·用verilog写的，基于查表法实现的LO ·精通verilog HDL语言编- up:in STD_LOGIC down:in STD_LOGIC run_stop:in STD_LOGIC wai_t: in std_logic_vector(2 downto 0) lift:in std_logic_vector(2 downto 0) ladd: out std_logic_vector(1 downto 0) ) end control
Update : 2025-02-17 Size : 17.82mb Publisher : liuzhou
[TCP/IP stack] CCD DL : 1: CCD数字相机的全代码，DMA方式读取FPGA，FIFO送入计算机，网口跑UDP协议-CCD digital camera the entire code, DMA mode to read FPGA, FIFO into the computer, I run UDP network protocol
Update : 2025-02-17 Size : 40kb Publisher : ccdd
[VHDL-FPGA-Verilog] DMA_8237A DL : 0: 经典DMA控制器8237A的VHDL设计，对设计DMA控制器有很高的参考价值。-Classic DMA controller 8237A of the VHDL design, the design of the DMA controller has a high reference value.
Update : 2025-02-17 Size : 12kb Publisher : neversee
[VHDL-FPGA-Verilog] DMA DL : 0: 针对QUARTUS的DMA的VHDL代码实现-DMA Controller Code in VHDL
Update : 2025-02-17 Size : 2kb Publisher : hejian
[Embeded-SCM Develop] NIOS_DMA_test DL : 0: NiosII范例,都是比较经典复杂的例程，很不错的-FPGA NIOSII SOPC
Update : 2025-02-17 Size : 16.41mb Publisher : yjh
[Software Engineering] CPU_Architecture DL : 0: Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks. External hardware accelerator is used for network packet processing. The common network tasks include CRC and Checksum calculations that are used for validation of data integrity in the network packets. The accelerator unit is able to perform a checksum and CRC calculation autonomously without CPU interactions using a build in DMA mechanism. -Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks. External hardware accelerator is used for network packet processing. The common network tasks include CRC and Checksum calculations that are used for validation of data integrity in the network packets. The accelerator unit is able to perform a checksum and CRC calculation autonomously without CPU interactions using a build in DMA mechanism.
Update : 2025-02-17 Size : 2.39mb Publisher : Amit Adoni
[VHDL-FPGA-Verilog] sdcard_mass_storage_controller_latest.tar DL : 0: 基于wishbone总线的SD Card IP Core,有Verilog和VHDL两种语言版本,包含了FIFO和DMA两种实现方式,是开源的IP Core-Based on the wishbone bus SD Card IP Core, there are two language versions of Verilog and VHDL, including the FIFO and DMA implemented in two ways, is open source IP Core
Update : 2025-02-17 Size : 2.17mb Publisher : 张亚群
[VHDL-FPGA-Verilog] Xilinx_PCIE_DMA DL : 1: Xilinx芯片所有关于PCI Express接口的DMA源代码，包含相关的配套的文档资料。-Xilinx chip on the PCI Express interface for all DMA source code, including relevant supporting documentation.
Update : 2025-02-17 Size : 29.41mb Publisher : caomeideweidao
[VHDL-FPGA-Verilog] XilinxPCIEDesignCourse DL : 0: xilinx官方推出的基于xilinx FPGA的PCIE设计的教程，包含DMA设计方法等，适合基于FPGA的PCIE开发人员参考和学习。-xilinx the official launch of the PCIE xilinx FPGA-based design tutorials, including the DMA design methods for FPGA-based information and learning PCIE developers.
Update : 2025-02-17 Size : 2.7mb Publisher : wuyedeniao
[VHDL-FPGA-Verilog] 6_DMA DL : 0: DMA用语FPGA开发的程序代码！欢迎大家来下载该程序！非常有利于学习！-DMA FPGA development code language! Welcome to download the program! Very conducive to learning!
Update : 2025-02-17 Size : 150kb Publisher : 王松
[Driver Develop] DMA-PCIe DL : 0: 利用XILINX的IP核设计DMA传输方式实现电脑和FPGA板之间数据传输文档，很有参考价值。-DMA design by using ips provides by XILINX ,make the communication between PC and FPGA possbile.
Update : 2025-02-17 Size : 2.22mb Publisher : minitu
[VHDL-FPGA-Verilog] 121114156PCIE_DMA_DDR3_verilog_design DL : 0: 基于FPGA的pcie dma设计，可参考应用。(FPGA based PCIe DMA design, you can refer to the application.)
Update : 2025-02-17 Size : 2.76mb Publisher : popezha
[Other] 基于Xilinx_PCIe_Core的DMA设计 DL : 0: 可以借鉴用于设计pcie,希望对大家有帮助(can used to design pcie systerm)
Update : 2025-02-17 Size : 2.22mb Publisher : ldx001001

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