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[VHDL-FPGA-Verilog] adma

Description: Wishbone dma ip core
Platform: | Size: 7168 | Author: liwen | Hits:

[VHDL-FPGA-Verilog] ide_control

Description: 三段式Verilog的IDE程序，但只有DMA部分，需要自己添加PIO的代码-Verilog three-step procedure of the IDE, but only parts of DMA, PIO required to add their own code
Platform: | Size: 2048 | Author: wang | Hits:

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