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Description: 数字锁相环DPLL实例程序，帮助理解PLL的结构和详细原理-DPLL DPLL examples of procedures to help understand the structure and PLL detailed Principle
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Size: 986 |
Author: 李向坤 |
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Description: DPLL由 鉴相器 模K加减计数器 脉冲加减电路 同步建立侦察电路 模N分频器 构成.
整个系统的中心频率(即signal_in和signal_out的码速率的2倍)
为clk/8/N. 模K加减计数器的K值决定DPLL的精度和同步建立时间,K越大,则同步建立时间长,同步精度高.反之则短,低.
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Size: 1386 |
Author: sharny |
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Description: Quantization effect on a 2nd order DPLL design
When quantization resoultion b varies, the DPLL has different outputs. This difference can be seen from step response, sine and other inputs (chirp as illustrative example).
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Size: 1240 |
Author: dairy |
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Description: 数字锁相环DPLL实例程序，帮助理解PLL的结构和详细原理-DPLL DPLL examples of procedures to help understand the structure and PLL detailed Principle
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Size: 1024 |
Author: 李向坤 |
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Description: 数字锁相环DPLL源程序，用cpld编写，展开后文件比较多，大家请耐心使用。谢谢，多多支持-DPLL source with cpld prepared after the start of more documents, please use patience. Thank you, the generous support!
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Size: 120832 |
Author: |
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Description: 数字琐相环DPLL的VERLOG代码，MODELSIM下的工程，有测试文件-digital phase-locked loop DPLL VERLOG code MODELSIM under the projects, a test document
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Size: 19456 |
Author: 刘仪 |
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Description: DPLL由 鉴相器 模K加减计数器 脉冲加减电路 同步建立侦察电路 模N分频器 构成.
整个系统的中心频率(即signal_in和signal_out的码速率的2倍)
为clk/8/N. 模K加减计数器的K值决定DPLL的精度和同步建立时间,K越大,则同步建立时间长,同步精度高.反之则短,低.-DPLL phase detector by the addition and subtraction counter modulus K synchronous pulse addition and subtraction circuit detection circuit establishing mode N divider constituted. The entire system of the center frequency (ie signal_in and signal_out the code rate of 2 times) for clk/8/N. Modulus K addition and subtraction of the K value of Counter DPLL decision accuracy and synchronization set-up time, K the greater the synchronization set-up time is long, synchronous and high accuracy. In contrast the short and low.
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Size: 1024 |
Author: |
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Description: Quantization effect on a 2nd order DPLL design
When quantization resoultion b varies, the DPLL has different outputs. This difference can be seen from step response, sine and other inputs (chirp as illustrative example).
Platform: |
Size: 1024 |
Author: dairy |
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Description: ＦＰＧＡ实现全数字锁相环，利用硬件描述评议verilog HDL，顶层文件ＤＰＬＬ．Ｖ-FPGA realization of all-digital phase-locked loop, using hardware description Convocation verilog HDL, the top-level document DPLL. V
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Size: 4096 |
Author: YP |
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Description: 一种可编程的全数字锁相环的丝线,可以用来做一个小的课程设计-A programmable DPLL thread can be used to do a small course design
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Size: 140288 |
Author: 国家 |
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Description: DPLL SIMULATION in MATLAB
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Size: 1024 |
Author: Bhavin |
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Description: dpll的verilog代码，完成数字锁相。用于时钟对准，位同步。-dpll the verilog code to complete the digital phase-locked. Alignment for the clock, bit synchronization.
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Size: 1024 |
Author: hsj |
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Description: Dpll source core ,it is very good for some one-Dpll source core,it is very good for some one
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Size: 9216 |
Author: yexianyang |
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Description: DPLL的源代码，包含了一个costas环的仿真
，供参考学习用。-Digital phase loop
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Size: 2048 |
Author: zb |
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Description: 该程序实现了用dpll对可满足问题的求解，-The program achieved the right to meet with dpll problem solving,
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Size: 2048 |
Author: 唐 |
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Description: 基于VHDL语言的DPLL电路的设计，给出了设计方案和部分源代码
-DPLL
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Size: 193536 |
Author: zhao peng |
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Description: 本文介绍了锁相环路的基本原理，并着重分析了数字锁相环的结构、原理。利用Verilog语言对数字锁相环的主要模块进行了设计，并用Modelsim软件进行仿真。最后给出了整个系统的仿真结果，验证设计的正确性，并在现场可编程门阵列FPGA上予以实现-dpll
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Size: 12288 |
Author: 卢迎 |
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Description: 应用matlab设计D触发器型的锁相环的设计的程序并对相位很频率进行性能图形比较-matlab desire Dpll
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Size: 1024 |
Author: 赵红玉 |
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Description: 数字锁相环，这里有个例子，可以借鉴看看，用simulink搭建的-dpll
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Size: 11264 |
Author: Shane |
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Description: 数字锁相环（DPLL）的介绍与硬件实现设计-Introduction and hardware design of Digital PLL (DPLL)
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Size: 1366016 |
Author: BenQlin |
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