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[Other resource] dpll

Description: ＦＰＧＡ实现全数字锁相环，利用硬件描述评议verilog HDL，顶层文件ＤＰＬＬ．Ｖ
Platform: | Size: 4731 | Author: YP | Hits:

[VHDL-FPGA-Verilog] dll11254

Description: 数字琐相环DPLL的VERLOG代码，MODELSIM下的工程，有测试文件-digital phase-locked loop DPLL VERLOG code MODELSIM under the projects, a test document
Platform: | Size: 19456 | Author: 刘仪 | Hits:

[Other Embeded program] verilogpll

Description: 用verilog语言编写的全数字锁相环的源代码,基于fpga平台-using Verilog language prepared by the DPLL the source code, they simply based on the platform
Platform: | Size: 3072 | Author: letheo | Hits:

[VHDL-FPGA-Verilog] ADPLL

Description: verilog ADPLL file with testbench.v
Platform: | Size: 25600 | Author: | Hits:

[Wavelet] verilogpll1234

Description: 基于verilog的全数字锁相环的设计，基于verilog的全数字锁相环的设计。-verilog DPLL the design, verilog based on the DPLL design.
Platform: | Size: 93184 | Author: li | Hits:

[ARM-PowerPC-ColdFire-MIPS] 8088verilog

Description: intel 8088 架构的verilog代码，可以综合下载，在fpga上实现8088调试。-intel 8088 verilog structure of the code can be integrated download, fpga achieved in 8088 debugging.
Platform: | Size: 240640 | Author: blueli | Hits:

[VHDL-FPGA-Verilog] dpll_demo

Description: 一个实现简单的数字锁相环Verilog代码，本人借鉴网上现有的代码后经修改在Cyclone II上调通实现，里面有ModelSim仿真成功的波形图-A simple digital PLL Verilog code, I draw on-line after the existing code, as amended, pass upward in the Cyclone II realized, there are successful ModelSim Simulation Waveform
Platform: | Size: 67584 | Author: | Hits:

[VHDL-FPGA-Verilog] DPLL_verilog

Description: 一阶全数字锁相环VERLOGIC程序代码，调试通过。-First-order DPLL VERLOGIC program code, debugging through.
Platform: | Size: 2048 | Author: 梁大法 | Hits:

[VHDL-FPGA-Verilog] dpll

Description: ＦＰＧＡ实现全数字锁相环，利用硬件描述评议verilog HDL，顶层文件ＤＰＬＬ．Ｖ-FPGA realization of all-digital phase-locked loop, using hardware description Convocation verilog HDL, the top-level document DPLL. V
Platform: | Size: 4096 | Author: YP | Hits:

[VHDL-FPGA-Verilog] FPGA-DPLL

Description: 基于FPGA实现的一种新型数字锁相环-FPGA-based realization of a new type of digital phase-locked loop
Platform: | Size: 181248 | Author: lixu | Hits:

[VHDL-FPGA-Verilog] dpll

Description: dpll的verilog代码，完成数字锁相。用于时钟对准，位同步。-dpll the verilog code to complete the digital phase-locked. Alignment for the clock, bit synchronization.
Platform: | Size: 1024 | Author: hsj | Hits:

[Communication-Mobile] dpll

Description: All Digital Phase-Locked Loop verilog source code
Platform: | Size: 1024 | Author: 李浩 | Hits:

[VHDL-FPGA-Verilog] DPLL

Description: 全数字锁相环的verilog设计，已通过仿真验证能迅速锁定相位-Digital phase loop lock design with verilog
Platform: | Size: 1024 | Author: yangyanwen | Hits:

[Other] dpll

Description: 本文介绍了锁相环路的基本原理，并着重分析了数字锁相环的结构、原理。利用Verilog语言对数字锁相环的主要模块进行了设计，并用Modelsim软件进行仿真。最后给出了整个系统的仿真结果，验证设计的正确性，并在现场可编程门阵列FPGA上予以实现-dpll
Platform: | Size: 12288 | Author: 卢迎 | Hits:

[VHDL-FPGA-Verilog] dpll

Description: 基于Verilog的数字锁相环。包括三个模块，数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
Platform: | Size: 668672 | Author: 栾帅 | Hits:

[Other] ver3

Description: 全数字锁相环的verilog代码，希望能有帮助-The DPLL verilog code, hoping to help! ! !
Platform: | Size: 956416 | Author: 解超 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 全数字锁相环的verilog源代码，用于FPGA开发全数字锁相环-DPLL verilog source code for FPGA development DPLL
Platform: | Size: 1024 | Author: wangxin | Hits:

[VHDL-FPGA-Verilog] verilog-pll

Description: 用verilog写的倍频电路 文件中介绍DP-The multiplier circuit file by verilog introduced DPLL
Platform: | Size: 1323008 | Author: loadziliao | Hits:

[VHDL-FPGA-Verilog] dpll

Description: 用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证-verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider
Platform: | Size: 6144 | Author: chi zhang | Hits:

[hardware design] dpll

Description: 数字锁相环 dpll的 编译通过,使用verilog HDL语言对锁相环进行基于FPGA的全数字系统设计,以及对其性能进行分析和计算机仿真的具体方法-Digital phase-locked loop dpll compiler through the use of verilog HDL language on the phase-locked loop FPGA-based digital system design, as well as its performance analysis and computer simulation of specific methods
Platform: | Size: 1024 | Author: 王铎皓 | Hits:
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