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[DSP programDSP-533M-ddr2RAM4C6455

Description: C6455 的 533M DDR2 ram 控制程序。完整代码,可以直接使用。-533M DDR2 ram the C6455 control procedures. Integrity of the code, can be used directly.
Platform: | Size: 10240 | Author: 付彦 | Hits:

[VHDL-FPGA-VerilogXil3SD1800A_MIG_simplifiedUI_vlog_v92

Description: verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
Platform: | Size: 908288 | Author: ma yirong | Hits:

[OtherTMS320C6455

Description: tms320c6455 High-Performance Fixed-Point DSP TMS320C64x+™ DSP Core Enhanced VCP2 Enhanced Turbo Decoder Coprocessor (TCP2) 64-Bit External Memory Interface (EMIFA) Four 1x Serial RapidIO® Links (or One 4x), DDR2 Memory Controller EDMA3 Controller (64 Independent Channels)-tms320c6455 High-Performance Fixed-Point DSP TMS320C64x+™ DSP Core Enhanced VCP2 Enhanced Turbo Decoder Coprocessor (TCP2) 64-Bit External Memory Interface (EMIFA) Four 1x Serial RapidIO® Links (or One 4x), DDR2 Memory Controller EDMA3 Controller (64 Independent Channels)...
Platform: | Size: 1605632 | Author: victor | Hits:

[DSP programddr

Description: 在TMS320DM6446 DSP环境下,对DDR2进行读写测试。-In the TMS320DM6446 DSP environment, reading and writing tests for DDR2.
Platform: | Size: 69632 | Author: 万传 | Hits:

[DSP programrty

Description: 近年来,随着DSP的快速发展,被广泛的应用于图像处理及目标定位[11][13][21]上,极大地提高图像处理的实时性。DSP主要用来实现扩展算法和数字信号处理的功能,其最典型的用途是实现数字图像处理算法。DSP芯片内采用大容量的SRAM作为系统的高速缓存,高达64位的数据总线带宽。在片外采用了目前流行的SDRAM、DDR2等高速大容量存储器的无缝连接,同时还支持SRAM、FIFO等各种类型的存储器,大大提高了图像的存储容量及速度。-In recent years, with the rapid development of DSP, has been widely used in image processing and target location [11] [13] [21], and greatly improve the image processing in real time. Mainly used to implement DSP algorithms and digital signal processing expansion of the function, the most typical use digital image processing algorithms. DSP chip with large-capacity SRAM cache as a system, up to 64-bit data bus bandwidth. Chip used in the popular SDRAM, DDR2 memory and other high-speed large-capacity seamless connection, and also supports SRAM, FIFO, and other types of memory, greatly improving the image storage capacity and speed.
Platform: | Size: 261120 | Author: 侯国强 | Hits:

[Special Effectss

Description: 近年来,随着DSP的快速发展,被广泛的应用于图像处理及目标定位[11][13][21]上,极大地提高图像处理的实时性。DSP主要用来实现扩展算法和数字信号处理的功能,其最典型的用途是实现数字图像处理算法。DSP芯片内采用大容量的SRAM作为系统的高速缓存,高达64位的数据总线带宽。在片外采用了目前流行的SDRAM、DDR2等高速大容量存储器的无缝连接,同时还支持SRAM、FIFO等各种类型的存储器,大大提高了图像的存储容量及速度。-In recent years, with the rapid development of DSP, has been widely used in image processing and target location [11] [13] [21], and greatly improve the image processing in real time. Mainly used to implement DSP algorithms and digital signal processing expansion of the function, the most typical use digital image processing algorithms. DSP chip with large-capacity SRAM cache as a system, up to 64-bit data bus bandwidth. Chip used in the popular SDRAM, DDR2 memory and other high-speed large-capacity seamless connection, and also supports SRAM, FIFO, and other types of memory, greatly improving the image storage capacity and speed.
Platform: | Size: 1499136 | Author: 侯国强 | Hits:

[DSP programddr

Description: 在TMS320DM6446 DSP环境下对DDR2进行读写测试-In TMS320DM6446 DSP environment, read and write test on the DDR2
Platform: | Size: 69632 | Author: LeeHY | Hits:

[DSP programddr2

Description: dsp tmsc6455 ddr配置例程-dsp tmsc6455 ddr configuration routines
Platform: | Size: 48128 | Author: 李凤 | Hits:

[DSP programddr

Description: TI公司 TMS320DM368 DSP的 DDR2 读写程序-TI' s TMS320DM368 DSP DDR2 read and write procedures
Platform: | Size: 71680 | Author: dlk | Hits:

[VHDL-FPGA-Verilogddr2

Description: 基于xilinx spartan -3A DSP的ddr2控制器-Based on the Xilinx Spartan-3A DSP DDR2 controller
Platform: | Size: 12134400 | Author: 朱义 | Hits:

[DSP programLab0201_ddr

Description: DDR2 数据存储实验,学习用 Code Composer Studio 观察、修改、填充 DSP 内存单元的方法-DDR2 Experimental data storage
Platform: | Size: 164864 | Author: zxcvbnm | Hits:

[matlabCali

Description: 时间交替并行ADC相位误差、偏置误差、增益误差的校正,ddr2 sdram内存条的控制,基于visual dsp-phase, offset and gain error calibration of time-interleaved ADCs, ddr2 sdram controlment
Platform: | Size: 35840 | Author: s | Hits:

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