Description: verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-modules, testBench the test Platform: |
Size: 2241 |
Author:seiji |
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Description: The purpose of this lab is to introduce the concept of FSMs with a datapath, and to
study the usage of more complex test benches. Also, we enforce a rudimentary design
methodology by assuming that the students are part of a bigger project, and have no
knowledge of VHDL-implementation of the datapath (made by a hypothetical other
group) other than its predefined Entity Interface until they come to the lab.
The rest of this document is structured as follows: Section 2 describes some prelimi-
nary reading and exercises that should be done before the lab. Section 3 details the
design tasks that should be carried out to pass this lab.
Platform: |
Size: 385307 |
Author:xingyazhou |
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Description: for FPGA IMPLEMENTATION,OUR DATAPATH CREATED FOR TWO BIRS MULTIPLICATION-for FPGA IMPLEMENTATION, OUR DATAPATH CREATED FOR TWO BIRS MULTIPLICATION Platform: |
Size: 15360 |
Author:ningchang2001 |
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Description: This a simple MIPS processor datapath written in VERILOG hardware language. You can see the signals when emulating in signalscan. Compile it with verilog in linux.-This is a simple MIPS processor datapath written in VERILOG hardware language. You can see the signals when emulating in signalscan. Compile it with verilog in linux. Platform: |
Size: 2048 |
Author:thesky |
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Description: MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j"
Mem.vhd - memory
buffer.vhd - buffer
ALUcon.vhd - Alu controller
pc.vhd - program counter
REG - registers-MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j"
Mem.vhd- memory
buffer.vhd- buffer
ALUcon.vhd- Alu controller
pc.vhd- program counter
REG- registers Platform: |
Size: 8192 |
Author:zi |
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Description: All writes e.g. Writes to device state (add remove datapath, port, set operations on vports, etc.), Writes to other state (flow table modifications, set miscellaneous datapath parameters, etc.) are protected by ovs_lock.
Platform: |
Size: 14336 |
Author:hasuiwen |
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