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[Embeded-SCM Develop] 16bit_booth_multiplier_STG DL : 0: verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-modules, testBench the test
Date : 2008-10-13 Size : 2.19kb User : seiji
[Other resource] xx_new4 DL : 0: The purpose of this lab is to introduce the concept of FSMs with a datapath, and to study the usage of more complex test benches. Also, we enforce a rudimentary design methodology by assuming that the students are part of a bigger project, and have no knowledge of VHDL-implementation of the datapath (made by a hypothetical other group) other than its predefined Entity Interface until they come to the lab. The rest of this document is structured as follows: Section 2 describes some prelimi- nary reading and exercises that should be done before the lab. Section 3 details the design tasks that should be carried out to pass this lab.
Date : 2008-10-13 Size : 376.28kb User : xingyazhou
[Other resource] datapath DL : 0: MIPS处理器的数据通道VHDL代码，可综合，可仿真，属硬件描述语言，集成电路设计代码
Date : 2008-10-13 Size : 1.47kb User : 陈丰
[OS program] 25175bm DL : 0: 学生报名管理系统功能简介: /Registration.asp 学生注册系统主文件报名内容{用户名,密码,确认密码,EMail,QQ号码 ,真实姓名 ,性别,年龄,家庭住址,电话,手机,身份证号码,密码提示问题,安全回答} /user_login.asp 通过注册的帐号：密码：验证码：进行登陆学生 /conn.asp 将此段改成你要的路径DataPath=\"/20070911baoming20/data/#123.mdb\" /admin/login.asp 后台admin admin进行登陆管理,密码是加MD5加密 md5双重加密，防SQL注入,分页技术,用户群删, /admin_index.asp 服务器基本信息显示 /logout.asp 后台退出
Date : 2008-10-13 Size : 249.54kb User : jjjja
[GUI Develop] students-manager DL : 0: 学生报名管理系统：报名内容{用户名,密码,确认密码,EMail,QQ号码 ,真实姓名 ,性别,年龄,家庭住址,电话,手机,身份证号码,密码提示问题,安全回答} /user_login.asp 通过注册的帐号：密码：验证码：进行登陆学生 /conn.asp 将此段改成你要的路径DataPath=\"/20070911baoming20/data/#123.mdb\" /admin/login.asp 后台admin admin进行登陆管理,密码是加MD5加密 md5双重加密，防SQL注入,分页技术,用户群删, /admin_index.asp 服务器基本信息显示 /logout.asp 后台退出
Date : 2008-10-13 Size : 467.69kb User : 老刘
[WEB Code] 25175baoming1 DL : 0: /Registration.asp 学生注册系统主文件报名内容{用户名,密码,确认密码,EMail,QQ号码 ,真实姓名 ,性别,年龄,家庭住址,电话,手机,身份证号码,密码提示问题,安全回答} 所有报名内容都要经过验证，互联网上细节做的到位的25175报名类软件 /user_login.asp 通过注册的帐号：密码：验证码：进行登陆学生 /conn.asp 将此段改成你要的路径DataPath=\"/20070911baoming20/data/#123.mdb\" 自己设置你的路径 /admin/login.asp 后台admin admin进行登陆管理,密码是加MD5加密 md5双重加密，防SQL注入,分页技术,用户群删, /admin_index.asp 服务器基本信息显示 /logout.asp 后台退出 conn.asp on error resume next 去掉自动设置路径匹配
Date : 2008-10-13 Size : 491.17kb User : 攀登者
[Graph program] 大屏幕拼接软件源码示例(Datapath版) DL : 0: 大屏幕拼接软件源码示例。适用于DATAPATH板卡。

Date : 2009-01-13 Size : 42.55kb User : stevenqq
[MPI] datapath DL : 0: MIPS处理器的数据通道VHDL代码，可综合，可仿真，属硬件描述语言，集成电路设计代码-MIPS processor data channel VHDL code can be integrated to simulation, a hardware description language, integrated circuit design code
Date : 2025-07-15 Size : 1kb User : 陈丰
[VHDL-FPGA-Verilog] datapath DL : 0: for FPGA IMPLEMENTATION,OUR DATAPATH CREATED FOR TWO BIRS MULTIPLICATION-for FPGA IMPLEMENTATION, OUR DATAPATH CREATED FOR TWO BIRS MULTIPLICATION
Date : 2025-07-15 Size : 15kb User : ningchang2001
[Other] ask10 DL : 0: This a simple MIPS processor datapath written in VERILOG hardware language. You can see the signals when emulating in signalscan. Compile it with verilog in linux.-This is a simple MIPS processor datapath written in VERILOG hardware language. You can see the signals when emulating in signalscan. Compile it with verilog in linux.
Date : 2025-07-15 Size : 2kb User : thesky
[VHDL-FPGA-Verilog] Datapaths DL : 0: vhdl source code for 8 bit datapath logic
Date : 2025-07-15 Size : 576kb User : utkarsh
[VHDL-FPGA-Verilog] Digital-Computer-Arithmetic-Datapath-Design-Using DL : 0: Digital Computer Arithmetic Datapath Design Using Verilog HDL
Date : 2025-07-15 Size : 1.09mb User : ali
[VHDL-FPGA-Verilog] VHDL-for-Datapath DL : 0: MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd - memory buffer.vhd - buffer ALUcon.vhd - Alu controller pc.vhd - program counter REG - registers-MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd- memory buffer.vhd- buffer ALUcon.vhd- Alu controller pc.vhd- program counter REG- registers
Date : 2025-07-15 Size : 8kb User : zi
[VHDL-FPGA-Verilog] Datapath DL : 0: datapath of 8bit synthesized risc processor
Date : 2025-07-15 Size : 2kb User : Mudi
[Other] counter-datapath DL : 0: the file of datapath,counter vhdl code
Date : 2025-07-15 Size : 2kb User : park kyoung han
[Linux-Unix] datapath DL : 0: Open vSwitch switching datapath for Linux.
Date : 2025-07-15 Size : 12kb User : zingyinsin
[VHDL-FPGA-Verilog] datapath DL : 0: 单片机PIC16C5X的datapath代码，包括ALU,alu_mux,w_reg和各个指令的代码-The datapath PIC16C5X microcontroller code, including ALU, alu_mux, w_reg and each instruction code
Date : 2025-07-15 Size : 2kb User : 泉哥哥
[Linux-Unix] datapath DL : 0: All writes e.g. Writes to device state (add remove datapath, port, set operations on vports, etc.), Writes to other state (flow table modifications, set miscellaneous datapath parameters, etc.) are protected by ovs_lock.
Date : 2025-07-15 Size : 14kb User : hasuiwen
[VHDL-FPGA-Verilog] DataPath DL : 0: datapath-datapath of Cpu
Date : 2025-07-15 Size : 1kb User : leee
[Other] DataPath DL : 0: Datapath PNG for the Model Sim example.
Date : 2025-07-15 Size : 63kb User : Gokul_4055

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