Description: SystemC片上系统设计的源代码：
书籍介绍：
SystemC是被实践证明的优秀的系统设计描述语言，它能够完成从系统到门级、从软件到硬件、从设计到验证的全部描述。SystemC 2.01已作为一个稳定的版本提交到IEEE，申请国际标准。
本书为配合清华大学电子工程系SystemC相关课程的教学而编写。全书分9章，内容包括：硬件描述语言的发展史；SystemC出现的历史背景和片上系统设计方法学概述；SystemC的基本语法；SystemC的寄存器传输级设计和SystemC的可综合语言子集，以及根据作者设计经历归结的RTL设计准则和经验；接口、端口和通道等SystemC行为建模实例——片上总线系统；SystemC与VHDL/Verilog HDL的比较；SystemC的验证标准和验证方法学；SystemC开发工具SystemC_win、WaveViewer等，以及使用MATLAB进行SystemC算法模块的验证。每一章都精心编写了课后习题以配合教学的需要。
本书可作为大学电子设计自动化（EDA）相关课程教材，也可供电子工程技术人员作为SystemC设计、应用开发的技术参考书。本书丰富的实例源代码特别适合初学者根据内容实际运行、体会，举一反三，以掌握SystemC进行应用系统设计。 -SystemC system on chip design source : books introduced : SystemC has been proven in practice is an excellent system design description language, it can be completed from the system level to the door, from hardware to software, from design to verification of all description. SystemC has 2.01 as a stable version submitted to the IEEE, the application of international standards. The book to tie in electronic engineering at Tsinghua University SystemC related courses and preparation of teaching. Book nine chapters, including : hardware description language development history; SystemC is the historical background and system-on-chip design methodology outlined; SystemC basic grammar; SystemC register-transfer-level design and synthesis of SystemC language subset, as well as design experience b Platform: |
Size: 2640896 |
Author:c.li |
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Description: VMM for SystemVerilog中文版
Synopsys推崇SystemVerilog的设计和验证语言
这是一本很好的电子书-VMM for SystemVerilog Chinese version of Synopsys highly SystemVerilog design and verification language This is a very good e-book Platform: |
Size: 435200 |
Author:stevephen |
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Description: systemverilog3.1a的中文版（chm）和英文版（pdf），IC设计和验证发展的大趋势，绝对物超所值，希望对IC设计者有所帮助-systemverilog3.1a the Chinese version (chm) and English (pdf), IC design and verification development trends, the absolute value for money, and they hope to help IC designers Platform: |
Size: 4560896 |
Author:Vallen |
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Description: Design and Test_Verilog HDL——EDA先锋工作室《设计与验证—Verilog HDL》配书源代码，很多使用的实例，并有说明，是学习Verilog 不可多得的好资料。-Design and Test_Verilog HDL- EDA pioneer studio design and verification-Verilog HDL book with source code, many examples and has made it clear that it is rare to learn Verilog good information. Platform: |
Size: 1887232 |
Author:ZY |
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Description: 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点 结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合 利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure and the basic hardware features, a brief introduction of the FIR filter the way to achieve the advantages and disadvantages of combining Altera s Stratix series of characteristics of the product, with a MAC based on the 8-order FIR digital filter design For example, given the use of Verilog hardware description language for digital logic design process and methods, and Quartus Ⅱ integrated development environment, prepared HDL code, for comprehensive utilization of Quartus Ⅱ emulator internal design so the impulse response simulation and verification. Platform: |
Size: 79872 |
Author:sundan |
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Description: The use of hardware description languages (HDLs) is becoming
increasingly common for designing and verifying FPGA designs.
Behavior level description not only increases design productivity, but also
provides unique advantages for design verification. The most dominant
HDLs today are Verilog and VHDL. This application note illustrates the
use of Verilog in the design and verification of a digital UART (Universal
Asynchronous Receiver & Transmitter). Platform: |
Size: 141312 |
Author:ltrko9kd |
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Description: system verilog 是国际流行的设计和验证语言，根据语言的特点分为两部分:for设计和for验证。另外一种书是介绍如何应用system verilog, 如果你要用syntem verilog, 推荐先读一下。-system verilog is popular hardware design and verification language. The languange compose of two part: systemverilog for desin , system verilog for test . in the rar package , a book introducing system verilog is recommanded. Platform: |
Size: 6114304 |
Author:jhv |
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Description: 本书作者为夏宇文，详细讲解了从算法设计与验证到硬件逻辑实现的过程，要求读者有一定的verilog基础-This book author XIA Yu-Wen gave a detailed account from algorithms to hardware logic design and verification of implementation process, requiring readers to have some basis for verilog Platform: |
Size: 832512 |
Author:neo |
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Description: Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard. Platform: |
Size: 1723392 |
Author:lucer_29a |
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Description: 一个很好的关于verilog的PPT
第1章 EDA设计与Verilog HDL语言概述
第2章 Verilog HDL基础与开发平台操作指南
第3章 Verilog HDL程序结构
第4章 VERILOG HDL语言基本要素
第5章 面向综合的行为描述语句
第6章 面向验证和仿真的行为描述语句
第7章 系统任务和编译预处理语句
第8章 VERILOG HDL可综合设计的难点解析
第9章 高级逻辑设计思想与代码风格
第10章 可综合状态机开发实例
第11章 常用逻辑的VERILOG HDL实现
第12章 XILINX硬核模块的VERILOG HDL调用
第13章 串口接口的VERILOG HDL设计-A good verilog of PPT on Chapter 1 of EDA Design and Verilog HDL language outlined in Chapter 2 based on Verilog HDL and development platform Operations Guide Chapter 3 Verilog HDL program structure VERILOG HDL languages Chapter 4 Chapter 5 for the basic elements of an integrated behavioral description statement in Chapter 6 for the verification and simulation of the behavior of the system described in Chapter 7 mission statements and prepared statements compiled in Chapter 8 VERILOG HDL design can be integrated Difficulties in Chapter 9, advanced logic design and coding style Chapter 10 Comprehensive state machine instance can be developed in Chapter 11 to achieve common logic VERILOG HDL Chapter 12 XILINX hard core module VERILOG HDL called Chapter 13 Serial Interface VERILOG HDL design Platform: |
Size: 27825152 |
Author:lyy |
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Description: Verilog数字系统设计——RTL综合.测试平台与验证 书中的所有源代码-Verilog Digital System Design- RTL synthesis. Test and verification platform for all the source code for the book Platform: |
Size: 8890368 |
Author:鲁智深 |
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Description: Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard.-Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard.
Platform: |
Size: 1723392 |
Author:bom |
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Description: Verilog HDL 数字设计与综合，夏宇闻译。本书重点关注如何应用verilog语言进行数字电路和系统的设计和验证，不仅讲解语法，更从基本概念讲起，逐渐过渡到编程语言接口以及逻辑综合等高级主题。-The design and synthesis of Verilog HDL digital, Xia Wen translation. The book focused on how to apply the verilog language for the design and verification of digital circuits and systems, not only explain the grammar, the more I start from the basic concept, and a gradual transition to advanced topics such as programming language interface and logic synthesis. Platform: |
Size: 12174336 |
Author:huluobo |
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Description: Verilog HDL--Guide to Digital Design and Synthesis (2ndEd) ASIC设计与验证领军人物 Samir Palnitkar的Verilog HDL优秀国外电子教材，国内夏宇闻老师那本Verilog教材的参考书籍，对于初学者有很大帮助！-Verilog HDL- Guide to Digital Design and Synthesis (2ndEd) ASIC design and verification leading figures Samir Palnitkar the Verilog HDL outstanding foreign e-learning materials, domestic Xia Wen teacher of the Verilog materials reference books of great help for beginners! Platform: |
Size: 3353600 |
Author:杨光 |
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Description: 全书共分4部分。第一部分共8章，即Verilog数字设计基础篇，可作为本科生的入门教材。第二部分共10章，即设计和验证篇，可作为本科高年级学生或研究生学习数字系统设计的参考书。第三部分为实践篇，共提供12个上机练习和实验范例。第四部分是语法篇，即Verilog 硬件描述语言参考手册；IEEE Verilog13642001标准简介，以反映Verilog语法的最新变化，可供读者学习、查询之用。-The book is divided into four parts. The first part of Chapter 8, Verilog Digital Design Basics, can be used as undergraduate introductory textbook. The second part of 10 chapters, the design and verification of papers, reference books can be used as a senior undergraduate students or graduate study digital system design. The third part is the practice papers, providing a total of 12 on exercises and experimental examples. The fourth part is the syntax articles, Verilog hardware description language reference manual Introduction to IEEE Verilog13642001 standards, to reflect the latest changes in the Verilog syntax for readers to learn inquiry. Platform: |
Size: 17120256 |
Author:虫虫 |
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Description: 《设计与验证-Verilog HDL》，很好的一本FPGA程序员用书，讲解很是详细，非常实用-" Design and Verification-Verilog HDL" , a very good one FPGA programmer with the book, to explain very detailed, very practical Platform: |
Size: 12794880 |
Author:qihongye |
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Description: 书本Verilog设计与验证的书本源码，望能帮助到有需要的人！-Books books Verilog design and verification code, hope to help the people in need! Platform: |
Size: 1941504 |
Author:英庆 |
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Search - Design and verification Verilog