Description: 本文在说明全数字锁相环的基础上，提出了一种利用FPGA设计一阶全数字锁相环的方法，并
给出了关键部件的RTL可综合代码，并结合本设计的一些仿真波形详细描述了数字锁相环的工作过程，最后对一些有关的问题进行了讨论。-In this paper, that all-digital phase-locked loop based on a FPGA design using first-order DPLL method, and gives the key components of the RTL code can be integrated and combined with the design of some of the detailed simulation waveform describes the working process of digital phase-locked loop, the last of some related issues were discussed. Platform: |
Size: 286720 |
Author:wangyunshann |
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Description: Verilog HDL与VHDL都是数字系统设计的硬件描述语言，VerilogHDL适合算法级，rtl，逻辑级，门级，而VHDL适合特大型的系统级设计。针对这些特点这两本书深入浅出的介绍了这两种语言。-Verilog HDL and VHDL design of digital systems is the hardware description language, VerilogHDL suitable algorithm level, rtl, logic level, gate-level, and large VHDL for system-level design. In response to these characteristics of these two books in simple terms to introduce the two languages. Platform: |
Size: 15562752 |
Author:龙英 |
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Description: i2cinterface.v是我自己写的一段verilog代码，在接口为I2C接口的芯片设计中用到。送去流过片，仅作参考用。
debussy和modelsim协同仿真.txt 用于debussy和modelsim协同仿真时参考
RTL Coding and Optimization Guide for use with Design Compiler.pdf
数提讲座（1）.wmv
数提讲座（2）.wmv这两个视频和一篇文档对数字IC前端设计师的设计提高很有帮助，如果你觉得你到瓶颈状态了，想提高的话，强烈建议好好看看。
ADVANCED ASIC CHIP SYNTHESIS中文翻译资料.ppt这也是我极力推荐的，相信学习dc的人都知道原英文文档。这个ppt相当于翻译版，对dc和pt中文详细阐述。
基于DDR SDRAM控制时序分析的模型.pdf
全定制单元时序模型的建立.pdf 这两篇文档是用作建议时序模型的时候用作参考，是我花了小money买的哦。
数字IC设计全程实例.pdf 本文介绍了基于标准单元库的深亚微米数字集成电路的自动化设计流程。此流程从设计的系统行为级描述或RTL 级描述开始，依次通过系统行为级的功能验证，设计综合，综合后仿真，自动化布局布线，到最后的版图后仿真.
-i2cinterface.v a section of my own writing verilog code for the I2C interface in the interface used in chip design. Sent to flow through the film, only for reference.
debussy and modelsim co-simulation. txt for debussy and modelsim co-simulation reference
RTL Coding and Optimization Guide for use with Design Compiler.pdf
Mention the number of lectures (1). Wmv
Mention the number of lectures (2). Wmv the two videos, and the document is useful for the digital front-end IC designers to improve the design capability. if you think you go to bottleneck, and want to improve, then it is strongly recommended a good look.
ADVANCED ASIC CHIP SYNTHESIS Chinese translation of the information. Ppt that is what I strongly recommend, I believe that everyone learning dc knows its original English document. This ppt is equivalent to its translations.It elaborates the dc and pt in Chinese .
DDR SDRAM control the timing analysis based on the model. Pdf
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Size: 20989952 |
Author:喻琪 |
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Description: The first three examples illustrate the difference between RTL FSMD model (Finite State Machine with Datapath buildin) and RTL FSM + DataPath model. From view of RT level design, each digital design consists of a Control Unit (FSM) and a Datapath. The datapath consists of storage units such as registers and memories, and combinational units such as ALUs, adders, multipliers, shifters, and comparators. Platform: |
Size: 1024 |
Author:dhanagopal |
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Description: In the semiconductor and electronic design industry, Verilog is a hardware description language (HDL) used to model electronic systems. Verilog HDL, not to be confused with VHDL (a competing language), is most commonly used in the design, verification, and implementation of digital logic chips at the register transfer level (RTL) of abstraction. It is also used in the verification of analog and mixed-signal circuits. Platform: |
Size: 28672 |
Author:nataraja |
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