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[Other resource] rece_7E

Description: HDLC控制接收数据开始标志7E和去零模块，用于FPGA与E1相接，Verilog HDL语言编写
Platform: | Size: 1954 | Author: 刘彻 | Hits:

[VHDL-FPGA-Verilog] rece_7E

Description: HDLC控制接收数据开始标志7E和去零模块，用于FPGA与E1相接，Verilog HDL语言编写-HDLC control began to receive data to the zero mark 7E and modules for use in FPGA and E1 phase, Verilog HDL language
Platform: | Size: 2048 | Author: 刘彻 | Hits:

[Web Server] prj

Description: bitfiles for T1/E1 analis in fpga
Platform: | Size: 109568 | Author: Artashes | Hits:

[VHDL-FPGA-Verilog] e1_vhdl

Description: 用VHDL在FPGA内部实现E1的接口，适合通讯相关专业硬件开发使用-Within the FPGA implementation using VHDL E1 interface, the hardware for communications-related professional development to use
Platform: | Size: 18432 | Author: 彭涛 | Hits:

[VHDL-FPGA-Verilog] ethtoe1

Description: 硕士论文 基于FPGA的Ethernet+over+E1接口芯片的设计与实现.pdf-master paper the design and implentation of Ethernet+over+E1
Platform: | Size: 1329152 | Author: ganzhhua | Hits:

[VHDL-FPGA-Verilog] 34342342432

Description: 基于FPGA的PCIE1接口设计与实现.pdf-the design and implmentation of PCI and E1 interface based on FPGA.
Platform: | Size: 2991104 | Author: ganzhhua | Hits:

[VHDL-FPGA-Verilog] V35interface-communicate

Description: V.35接口与E1接口之间转换的基本原理,介绍了E1信道分时隙通信的基本过程，叙述了基于FPGA用VHDL和QuartusII来仿真本系统设计与实现的过程。-V.35 interface and E1 interface to convert between the basic principles of E1 channel introduces the basic process of communication sub-time slot, described by VHDL and FPGA-based QuartusII to simulate the system design and implementation process.
Platform: | Size: 1323008 | Author: 汪涵 | Hits:

[VHDL-FPGA-Verilog] bert

Description: 误码测试仪，基于FPGA的E1口误码测试仪-BER tester, based on FPGA-E1 port BER tester
Platform: | Size: 743424 | Author: 弓长 | Hits:

[VHDL-FPGA-Verilog] e1framerdeframer

Description: E1成帧器和解帧器的FPGA实现源码，测试可用-E1 Framer deframer
Platform: | Size: 35840 | Author: lijunwen | Hits:

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